SST89E54RDA-33-C-TQIE View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
Manufacturer
SST89E54RDA-33-C-TQIE Datasheet PDF : 84 Pages
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FlashFlex MCU
SST89E54RD2A/RDA / SST89E58RD2A/RDA
SST89V54RD2A/RDA / SST89V58RD2A/RDA
Data Sheet
4.2.4.7 Prog-SC0, Prog-SC1
Prog-SC0 command is used to program the SC0 bit. This
command only changes the SC0 bit and has no effect on
BSEL bit until after a reset cycle.
SC0 bit previously in un-programmed state can be pro-
grammed by this command. The Prog-SC0 command
should reside only in Block 1 or external code memory.
Prog-SC1 command is used to program the SC1 bit. This
command only changes the SC1 bit and has no effect on
SFCF[1] bit until after a reset cycle.
SC1 bit previously in un-programmed state can be pro-
grammed by this command. The Prog-SC1 command
should reside only in Block 1 or external code memory.
IAP Enable
ORL SFCF, #40H
Set-up Enable-Clock-Double
MOV SFAH, #55H
MOV SFDT, #0AAH
Program
Enable-Clock-Double
Polling scheme
MOV SFCM, #08H
Program
Enable-Clock-Double
Interrupt scheme
MOV SFCM, #88H
IAP Enable
ORL SFCF, #40H
Polling SFST[2]
indicates completion
INT1# Interrupt
indicates completion
1339 F15.0
FIGURE 4-8: Enable-Clock-Double
Set-up Program SC0
MOV SFAH, #5AH
MOV SFDT, #0AAH
Program SC0 or SC1 -
Polling scheme
MOV SFCM, #09H
Set-up Program SC1
MOV SFAH, #0AAH
MOV SFDT, #0AAH
Program SC0 or SC1 -
Interrupt scheme
MOV SFCM, #89H
4.2.5 Polling
A command that uses the polling method to detect flash
operation completion should poll on the FLASH_BUSY bit
(SFST[2]). When FLASH_BUSY de-asserts (logic 0), the
device is ready for the next operation.
MOVC instruction may also be used for verification of the
Programming and Erase operation of the flash memory.
MOVC instruction will fail if it is directed at a flash block that
is still busy.
Polling SFST[2]
indicates completion
INT1# Interrupt
indicates completion
1339 F14.0
FIGURE 4-7: Prog-SC0 and Prog-SC1
4.2.4.8 Enable-Clock-Double
Enable-Clock-Double command is used to make the MCU
run at 6 clocks per machine cycle. The standard (default) is
12 clocks per machine cycle (i.e. clock double command
disabled).
4.2.6 Interrupt Termination
If interrupt termination is selected, (SFCM[7] is set), then
an interrupt (INT1) will be generated to indicate flash opera-
tion completion. Under this condition, the INT1 becomes an
internal interrupt source. The INT1# pin can now be used
as a general purpose port pin and it cannot be the source
of External Interrupt 1 during in-application programming.
In order to use an interrupt to signal flash operation termi-
nation. EX1 and EA bits of IE register must be set. The IT1
bit of TCON register must also be set for edge trigger
detection.
©2007 Silicon Storage Technology, Inc.
40
S71339-01-000
1/07
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