Data Sheet
Serial Port Control Register (SCON)
Location
7
98H
SM0/FE
6
SM1
5
SM2
FlashFlex MCU
SST89E54RD2A/RDA / SST89E58RD2A/RDA
SST89V54RD2A/RDA / SST89V58RD2A/RDA
4
3
2
1
REN
TB8
RB8
TI
0
Reset Value
RI
00000000b
Symbol
FE
SM0
SM1
Function
Set SMOD0 = 1 to access FE bit.
0: No framing error
1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to
be cleared by software.
SMOD0 = 0 to access SM0 bit.
Serial Port Mode Bit 0
Serial Port Mode Bit 1
SM2
REN
TB8
RB8
TI
RI
SM0
0
0
1
SM1
0
1
0
Mode
0
1
2
1
1
3
1. fOSC = oscillator frequency
Description
Shift Register
8-bit UART
9-bit UART
9-bit UART
Baud Rate1
fOSC/6 (6 clock mode) or
fOSC/12 (12 clock mode)
Variable
fOSC/32 or fOSC/16 (6 clock mode)
or
fOSC/64 or fOSC/32 (12 clock mode)
Variable
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI
will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and
the received byte is a given or broadcast address. In Mode 1, if SM2 = 1 then RI will not
be activated unless a valid stop bit was received. In Mode 0, SM2 should be 0.
Enables serial reception.
0: to disable reception.
1: to enable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as
desired.
In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the
stop bit that was received. In Mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at
the beginning of the stop bit in the other modes, in any serial transmission, Must be
cleared by software.
Receive interrupt flag. Set by hardware at the end of the8th bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial reception (except see
SM2). Must be cleared by software.
©2007 Silicon Storage Technology, Inc.
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