M4640-19 View Datasheet(PDF) - Conexant Systems

Part Name

Description

Manufacturer

M4640-19

Baseband Processor for GSM Applications

Conexant Systems 

M46

Baseband Processor

Technical Description

The BP is a dual-core device consisting of an ARM7 THUMB

microcontroller core, a Conexant proprietary DSP core, and all

the digital control circuitry required in a GSM handset. The

following sections describe the operation and programming of

each of the functional blocks in the BP. Table 2 specifies the

address and default value for each of the registers in the device.

Note that the table specifies the value of each register before

the BP IROM code is executed.

ARM7 THUMB Core

The ARM7 THUMB core is a member of the Advanced RISC

Machines (ARM) family of general purpose 32-bit

microcontrollers that offer high performance with very low power

consumption. The ARM architecture is based on RISC principles

with a simple yet powerful instruction set. This simplicity enables

high instruction throughput and rapid real-time interrupt

response.

Pipelining is used extensively to ensure that all parts of the

processing and memory systems can operate continuously.

While one instruction is being executed, the next instruction is

being decoded and a third is being fetched from memory.

For further information on ARM7 THUMB please refer to the

ARM7TDMI data sheet published by ARM.

Internal Memory

The BP is supported by 12 kB of Internal RAM (IRAM) and 16

kB of Internal ROM (IROM). Both the IRAM and the IROM

directly interface to the 32-bit data and address buses from the

microcontroller core.

The IROM contains the embedded firmware which is executed

on power up. The IRAM is used for data storage during run time.

System Integration Unit (SIU)

The SIU is used to interface the 32-bit ARM bus to 8, 16, or 32-

bit memory and peripherals connected to the External

Expansion Bus (EXB) and Internal Peripheral Bus (IPB). Since

the ARM only interfaces to 32-bit devices, the SIU formats the

address and data to and from the ARM to allow 8, 16, or 32-bit

data transfers.

The SIU also performs address decoding to generate internal

and external chip select signals. These peripherals can be

internal to the BP or external. Internal peripherals (such as the

pulse width modulator) interface to the IPB while external

peripherals (such as system Flash memory) interface to the

EXB. The SIU performs the following main functions:

• Generates the required internal or external chip selects

• Formats the address bus and data bus for 8, 16 or 32-bit

transfers

Separating the buses minimizes power dissipation since only the

required bus lines are driven at any one time.

Internal Peripheral Bus (IPB)

The IPB interfaces to internal peripherals on the BP. The bus

supports both 8-bit and 16-bit peripherals. The bus is only active

when one of the internal peripherals is being accessed; if a

device on the EXB is being accessed, there is no activity on the

IPB.

External Expansion Bus (EXB)

The EXB allows external memory devices such as flash and

SRAM to be connected to the BP. Internal to the BP, the EXB is

connected to the SIU. The device features a 16-bit data bus

D[15:0] and a 22-bit address bus A[21:0].

Besides the address and data buses, the EXB also consists of

the following control signals:

• READ – active low read strobe that is asserted while data

is read from the external peripheral.

• WRITE – active low write strobe that is asserted while data

is being written to the external peripheral.

• CS[4:0] – configurable chip select signals.

• BS[1:0] – active low upper byte/lower byte select signals.

These are used when the BP is transferring byte wide data

to/from 16-bit peripherals. The polarity of these signals is

programmable.

Note that the BP always produces a byte address. When word

data (32-bit data) is transferred, A[1:0] bits are always low (set

to “0”), and when half word data (16-bit data) is transferred, the

A[0] bit is always low (set to “0”).

The timing diagrams for read and write accesses over the EXB

are shown in Figures 3 and 4, respectively. Figure 3 shows a

read from a 16-bit external device that requires two wait states.

Figure 4 shows a write to a 16-bit external device that requires

two wait states.

Note that the ARM clock signal is internal to the device and is

not output on any of the device pins.

Table 3 provides the values for all of the timing parameters.

Chip Select Signals __________________________________

The BP has five chip select signals. Two of these ,CS0 and

CS1, are on dedicated pins while the other three are multiplexed

with General Purpose Input Output (GPIO) signals.

Each of the chip select signals has a configuration register.

Each register is 16 bits wide but only the least significant 9 bits

are used. The function of each register bit is shown in Table 4.

The address and default values for the Chip Select Signal

Registers are specified in Table 2.

6

June 14, 2000

Conexant

Proprietary Information and Specifications are Subject to Change

100779C

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