M4640-19 View Datasheet(PDF) - Conexant Systems
Part Name
Description
Manufacturer
M4640-19 Datasheet PDF : 47 Pages
| |||
Baseband Processor
M46
SIM Interface Registers _______________________________
The following registers are described in this section:
• SIM Control Register
• SIM Status Register
• SIM Interrupt Enable Register
• SIM Interface Registers
• SIM Control Register
The address and default values for the SIM Interface Registers
are specified in Table 2.
SIM Control Register. The SIM Control Register controls the
operation of the SIM interface. The register is 32 bits wide. The
function of each of the bits in this register is described in
Table 26.
SIM Status Register. The SIM Status Register provides
information on the status of the SIM interface. If a SIM interrupt
is received by the ARM, reading this register indicates the
source of the interrupt. If the bit is set to a “1,” the associated
condition has occurred. The register is eight bits wide. The
function of each of the bits in this register is described in
Table 27.
SIM Interrupt Enable Register. The SIM Interrupt Enable
Register is used to mask the SIM interrupts. Each of the SIM
interface conditions that can generate a SIM activity interrupt
has an associated bit in this register which can be used to
enable or disable the generation of the interrupt if the condition
occurs. The register is eight bits wide. The function of each of
the bits in this register is described in Table 28.
SIM Output Buffer. The SIM Output Buffer is used to store the
data to be transmitted over the SIM interface.
SIM Input Buffer. The SIM Input Buffer is used to store the data
received over the SIM interface.
DSP Core
The DSP core is a dedicated DSP processor core that
implements all the physical layer (Layer 1) signal processing
required by a GSM-based handset. The DSP core
communicates with the controller core via the Dual Port RAM
(DPRAM) memory. The DSP also interfaces to the IA.
Dual Port Memory (DPRAM)
The DSP and ARM cores communicate via the DPRAM. On the
ARM side, the DPRAM interfaces to the IPB. Instructions and
information are passed between the two cores by writing to and
reading from the device DPRAM.
Control Interface
The control interface is a four-wire serial interface that provides
an interface between the BP and Conexant’s Integrated Analog
(IA) device. The interface is a high speed, synchronous, full
duplex, serial communications link. The interface is connected to
the DSP of the BP.
The control interface consists of the following signals:
• CNTRLCLK: 3.9 MHz clock signal output from the BP. This
is the clock signal for the interface.
• CNTRLRT: indicates the start and end of a
communications session. This signal is output from the BP.
• CNTRLDAT: serial output data from the BP.
• RSPNSDAT: serial data input to the BP.
The BP is the bus master for the interface. It initiates all
communications over the interface. Using this port, the BP can
perform the following functions:
1. Send control information to configure the operation of the
IA device.
2. Send bursts of transit data to the IA device for modulation.
3. Read contents of the IA Registers.
4. Figure 17 shows the signal sequence for write and read
operations over the control interface.
Codec Interface
The Codec interface is a four-wire serial interface that provides
an interface between the BP and the IA device. The interface is
a high speed, synchronous, full duplex, serial communications
link. The interface is connected to the DSP of the BP.
The Codec interface consists of the following signals:
• CDCCLK: 4 MHz input clock.
• CDCRATE: 8 kHz input framing signal.
• ENCDRDAT: serial data input to the BP. The bit rate is the
same as the CDCCLK rate (4 Mbps). The word rate is the
same as the CDCRATE signal (8 kwps). Words are 16 bits
wide.
• DCDRDAT: serial data output from the BP. The bit rate is
the same as the CDCCLK rate (4 Mbps). The word rate is
the same as the CDCRATE signal (8 kwps). Words are 16
bits wide.
When a voice call is in progress, the following occurs:
1. In the receive path, digitized audio samples are sent out
from the BP using the Codec interface. The digitized
samples are converted to an analog signal by the IA and
used to drive the handset speaker.
2. In the transmit path, the IA device converts the analog
output from the handset microphone into digital samples
that are sent to the BP using the Codec interface. The DSP
processes the samples for transmission by the handset RF
subsystem.
Figure 18 shows the timing diagram for the BP Codec interface.
100779C
Conexant
Proprietary Information and Specifications are Subject to Change
37
June 14, 2000
|
|
Share Link: 