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M4640-19 View Datasheet(PDF) - Conexant Systems

Part NameDescriptionManufacturer
M4640-19 Baseband Processor for GSM Applications Conexant
Conexant Systems Conexant
M4640-19 Datasheet PDF : 47 Pages
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M46
Table 23. Serial Bus Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Input High voltage
VIH
1.5
Input low voltage
VIL
Output high voltage
VOH
@ 500 µA IOH (Note 1)
2.4
Output low voltage
VOL
@ 3.2 mA IOL (Note 2)
Note 1: IOH is the maximum source current for a “1” output.
Note 2: IOL is the maximum sink current for a “0” output.
Typical
Baseband Processor
Max
Units
V
0.5
V
V
0.4
V
The bus only allows for byte-wide data transfers. An unrestricted
number of bits can be transferred between each start and stop
condition. The MSB is transmitted first.
After each byte transfer, the bus master generates an
acknowledge-related clock pulse. During this clock pulse, the
party that received the data must acknowledge that the data has
been received by pulling the SRLDATA line low (the transmitter
releases the SRLDATA line during this clock period to allow the
receiver to drive the line).
All data transactions between bus master and the bus slave are
initiated when the BP issues the Serial Bus Start condition. The
BP then sends the device address over the SRLDATA line. The
device address consists of seven bits of address and one bit
that specifies whether the operation is a read or write (from the
perspective of the bus master).
After the device address, the register address is sent by the bus
master. Following the register address, the data is placed on the
bus by the BP (write operation) or the bus slave (read
operation). If more than one byte of data is being transferred,
the register address is the starting address and subsequent
bytes are read from or written to sequential registers.
Figures 13 through 16 shows the sequence of events for single
or multiple byte read and write operations over the Conexant
serial bus.
Serial Bus Registers _________________________________
Two registers control the operation of the Conexant serial bus
data and clock signals. The address and default values for the
Serial Bus Registers are specified in Table 2.
Serial Data Register. The Serial Data Register is used to
specify the logic level of the serial data output. Writing to bit [0]
of this register places the written logic level on the serial data
pin. Reading bit [1] of the register returns the actual logic level of
the serial data pin. All other bits in this register are unused.
Serial Clock Register. The Serial Clock Register is used to
specify the logic level of the serial clock output. Writing to bit [0]
of this register places the written logic level on the serial clock
pin. Reading bit [1] of the register returns the actual logic level of
serial clock pin. All other bits in this register are unused.
SIM Interface
The BP provides a functional interface to the handset SIM card.
Since the BP nominally operates at 2.8 V and produces 2.8 V
logic levels, external voltage level translation circuitry is
necessary to interface with a 3 V SIM card.
The SIM interface is a half duplex, serial synchronous data link
which is fully described in sections 11.11 and 11.12 of the
European Telecommunications Standard Institute (ETSI) GSM
specifications.
The BP generates a number of SIM interface signals some of
which are required by the ETSI definition of the SIM interface
(after the external voltage translation circuitry, if required) and
some of which implement auxiliary functions required for
Conexant’s implementation of the SIM Interface. Table 25
provides a summary of these interface signals and their
functions.
For the SIM signals that are multiplexed with GPIO signals, the
appropriate I/O select bit must be set. See the GPIO section of
this Data Sheet for more information.
SIM Interrupts ______________________________________
Two different interrupts can be generated by the SIM interface
circuitry :
SIM timer interrupt
SIM activity interrupt
The SIM timer interrupt is generated when a time out condition
occurs. General purpose timer A is used to detect that a time
out has occurred. The timer can use the SIM system clock or
the SIM Elementary Time Unit (ETU) clock as an input. See the
General Purpose Timers section of this Data Sheet for more
information.
The SIM activity interrupt is generated when a recognized error
has occurred on the SIM interface. Each of these interrupts can
be individually enabled or disabled and are described in the
section on the SIM Interrupt Enable Register. If the SIM activity
interrupt is generated, the ARM can read the SIM Status
Register to determine the cause of the interrupt.
34
June 14, 2000
Conexant
Proprietary Information and Specifications are Subject to Change
100779C
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