Duty Cycle Register = 40
Counter Register = 100
20 40 60 80
20 40 60
In this example the duty cycle of the Tone signal is 60:40 (mark:space).
Regardless of the value of the duty cycle, the frequency of the Tone signal is
3.9 MHz/100 = 39 kHz.
Figure 10. Generation of PWM Mod Pulse Train
Table 16. Example Generation of the Tone Signal
Programmable Parameters :
Clock Divider Register = 250
Data Pattern Shift Register = 0xF0F0F0F0F0F0F0 (11110000111100001111000011110000b)
Calculation of Tone Frequency :
Clock Divider Input Clock = 1.95 MHz
Clock Divider Output = 1.95 MHz/250 = 7800 Hz (F)
Data Pattern Frequency = F/32 = 7800 Hz/32 = 243.75 Hz
With the above data pattern there are four signal cycles per data pattern cycle. Therefore, the frequency of Tone is:
243.75 Hz × 4 = 975 Hz
and the duty cycle of Tone is 50%
The Clock Divider Register is a programmable, 10-bit register.
The divider circuit divides down the 1.95 MHz input to the circuit
by the value of the register to yield an output signal with
frequency F. The output from the divider is used to clock the
Data Pattern Shift Register.
The Data Pattern Shift Register is a 32-bit serial shift register.
The contents of the programmable Data Pattern Latch Register
are downloaded to the Data Pattern Shift Register to set the
initial value of the shift register.
The output from the shift register is the tone pulse train, Tone.
This output is also fed back to the register input so that the
same series of 32 bits are continuously cycled through the
register. The data pattern is cycled at a frequency of f2/32.
An example of the generation of the Tone signal is shown in
The Mod and Tone pulse trains are ANDed to generate the
output from the annunciator circuit.
PWM Control Registers_______________________________
Table 17 shows the address and function of each of the PWM
registers. The default value of each of the registers is specified
in Table 2.
The Autobaud circuit monitors the SDS_RX input and
automatically detects the baud rate of the data received,
whether the data is formatted into seven or eight-bit words and
whether the parity is odd or even. There are certain restrictions
on the baud rate, word length, and characters that can be
When the Autobaud block is enabled, the ARM microcontroller
configures all the SDS port parameters except for the baud rate,
word length, and parity, which are provided by the Autobaud
June 14, 2000
Proprietary Information and Specifications are Subject to Change