IrDA Registers ______________________________________
There are two IrDA registers:
• Pulse Length Register
• Divider Ratio Register
IrDA Pulse Length Register. The IrDA Pulse Length Register
is used to set the length of the Tx pulse and the expected
duration of the Rx pulse. Bits [3:0] set the length of the Tx pulse.
The duration of the pulse is calculated as:
(Bits [3:0] + 1) × system clock cycle
For example, if the bits are set to 0x0F, the duration of the pulse
(15 + 1) ×
= 4.1 µsec
Bits [7:4] set the expected length of the Rx pulse. A pulse
received on the SDS_RX pin must be of this duration for the
Pulse Stretcher to generate a “0” on the SDS_RX pin. The
expected pulse duration is calculated the same as the Tx pulse
Bits [15:8] of the IrDA Pulse Length Register are reserved.
IrDA Divider Ratio Register. The IrDA Divider Ratio Register is
used to set the IrDA baud rate. The IrDA circuit derives the
interface bit period from PTG A, which is used to generate
timing for the SDS port. Bits [0:3] of this register set the baud
rate of the IrDA circuit. The baud rate is calculated as:
(bits[3 : 0] + 1)
The address and default values for the IrDA Registers are
specified in Table 2.
Cyclic Redundancy Check (CRC) Block _________________
The CRC block is used to perform error checking on blocks of
data. The microcontroller writes a sequence of byte-wide data to
the CRC Data Register, which calculates an output polynomial
based on the input sequence.
Before writing the data sequence, the output polynomial is reset
to 0xFFFF by writing to the CRC Reset Register. The output
polynomial can be read at any time and is typically appended to
a block of data so that the receiving entity can determine if there
were errors in the received data.
Reading from the CRC Data Register gives the output
The address and default values for the CRC Registers are
specified in Table 2.
The DMA Controller allows blocks of data to be transferred
directly between peripherals and memory. The maximum block
size that can be transferred is 2 KB.
When a DMA transfer is required, the ARM sets up the DMA
Controller with the block starting address and the block finishing
address. If a number of DMA transfers are requested at the
same time, the DMA Controller determines which has the
There are five DMA channels that are assigned as follows :
• DMA Channel 0 - Transfer data from the SDS serial port to
the main memory.
• DMA Channel 1 - Transfer data from the Debug serial port
to the main memory.
• DMA Channel 2 - Transfer data from the main memory to
the SDS serial port.
• DMA Channel 3 - Transfer data from the main memory to
the Debug serial port.
• DMA Channel 4 - Transfer data from the main memory to
the SIM interface.
The highest priority is Channel 0 and the lowest priority is
During the DMA transfer, the DMA Controller assumes control of
the bus and communicates with the SIU to allow the data to be
transferred directly between the memory and the peripheral.
After each data transfer, the value in the DMA Address Register
(originally loaded with the block starting address) is
incremented. When the block finishing address is reached, the
DMA Controller ceases data transfer after the current transfer
has been completed.
The DMA registers are used to set up the DMA operation. The
address and default values for the DMA Registers are specified
in Table 2.
DMA Address Register. Each DMA channel has a dedicated
Address Register. The Address Register is written to by the
ARM to set the starting address of the block to be transferred.
After each DMA data transfer, the value in the register is
incremented. The ARM writes to bits[0:23] to set up the address
but only bits[0:10] are incremented after each DMA data
June 14, 2000
Proprietary Information and Specifications are Subject to Change