Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

M4640-19 View Datasheet(PDF) - Conexant Systems

Part Name
Conexant Systems Conexant
M4640-19 Datasheet PDF : 47 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
Baseband Processor
Block Size
Table 2. BP Register Addresses (6 of 6)
SIM Interface
R/W SIM Control
SIM configuration
R/W SIM Status
Stores the current status of the SIM Interface.
R/W SIM Interrupt Enable
Enable/disable SIM Interrupt sources.
R/W SIM Output Buffer
Data to be transmitted over the SIM interface is
written to this buffer.
R/W SIM Input Buffer
Data received over the SIM interface is stored in
this buffer.
Default Value
20D1 7420
Byte Select Signals __________________________________
The byte select signals, BS[1:0], are used to transfer byte wide
data to and from 16-bit peripherals. When BS[0] is asserted, it
indicates that data is on bits D[7:0]; if BS[1] is asserted, data is
on bits D[15:8]. Both of these signals are active low.
During write operations to 16-bit peripherals, the byte select
signals must be connected to the corresponding pins on the
peripheral. These signals allow each 8-bit half of the 16-bit
peripheral register to be written to independently. This is
required since the ARM compiler may generate two byte
transactions when accessing a 16-bit peripheral instead of a
single half word (16-bit) transfer.
The polarity of the byte select signals is programmable. Bit [15]
of the SIU Configuration Register controls the polarity of these
signals. If this bit is set to “0,” the signals are active low. If this
bit is set to “1,” the bits are active high.
Clock Generation and Phase Locked Loop
The BP clock generation circuitry takes a 3.9 MHz square wave
system clock input, buffers it, and routes it to the internal
peripherals. Each of the peripherals has a dedicated clock
enable signal so that the clock signal can be turned off when the
peripheral is not in use.
The 3.9 MHz signal is also routed to the Phase Locked Loop
(PLL) circuitry which generates both the ARM and DSP clock
Clock Enables ______________________________________
Each of the device circuitry blocks has a dedicated clock enable
signal. This allows the clock signal to the circuitry block to be
turned off when it is not in use. The clock enable signals are
controlled by the contents of the Clock Control Register. If a
particular bit is set to “1,” the clock to the associated block is
turned on; if the bit is set to “0,” the clock is turned off. Table 5
describes the function of each bit in this register.
If a “0” is written to a specific bit, the associated clock will go low
at the next high-to-low transition of the system clock and stay
low until it is enabled again.
If a “1” is written to a specific bit, the associated clock will be
turned on at the next low-to-high transition of the system clock.
The address and default settings for the Clock Control Register
are specified in Table 2.
PLL Operation ______________________________________
A functional block diagram of the PLL is shown in Figure 5.
The system clock input (3.9 MHz) is divided down by the division
factor, P. This factor is a 2-bit number with a value of 2. The
output from this divider is input to the PLL block, which
generates an output at N times the input frequency, where N is
the multiplying factor (the value of N is 20). The PLL output is
input to the DSP core. The PLL output is also divided down by a
factor, M, to generate the ARM clock. The value of M is 2.
ARM Interrupt Controller
The ARM core can handle two interrupts:
Fast Interrupt Request (FIQ)
Interrupt Request (IRQ)
The FIQ has a higher priority than the IRQ. The IRQ is masked
when an FIQ sequence is entered. In the case of an FIQ
interrupt, fewer registers are required to be saved to memory.
Therefore, switching into the interrupt handler is slightly faster.
All possible interrupt sources (internal and external) are routed
to the Interrupt Controller, which generates either the FIQ or
IRQ interrupt.
Interrupt Controller Registers _________________________
The address and default settings for the Interrupt Controller
Registers are specified in Table 2.
June 14, 2000
Proprietary Information and Specifications are Subject to Change
Direct download click here


Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]