28222-14 View Datasheet(PDF) - Conexant Systems

Part Name

Description

Manufacturer

28222-14

ATM Transmitter/Receiver with UTOPIA Interface

Conexant Systems 

2.0 Functional Description

2.2 Line Framers

CN8223

ATM Transmitter/Receiver with UTOPIA Interface

The input timings are all similar: RXDATI and RXSYI are sampled on the

falling edge of the input clock; and the low-to-high transition of the sync signal

occurs during the interval of the frame bit for DS1 and DS3, with the first bit of

time slot 0 for E1, and the first bit of the frame-alignment signal for E3. For

brevity, only the DS1 timing is illustrated (Figure 2-11). The timing on this

interface is similar to the timing on the transmit interface. It is compatible with

Conexant framers. The data and sync inputs can be sampled on the rising edge of

the input clock by setting Invert RX Clock Sampling [bit 8] of CONFIG_3

[0x02].

In all framed, serial line formats, the content of the framing bit positions is

ignored. RXSYI does not need to be present every frame; it can be applied at any

submultiple of the frame rate (e.g., once every ESF superframe for DS1).

Figure 2-11. Receiver DS1 Line Interface Timing

RXCKI

RXSYI

RXDATI

78 S 2 3 4 5 6 7 8 FS 2 3 4 5 67

Channel 24

Channel 1

2-12

Conexant

100046C

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