28233-11 View Datasheet(PDF) - Conexant Systems
Part Name
Description
Manufacturer
28233-11 Datasheet PDF : 161 Pages
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1.0 Product Description
1.9 Logic Diagram
Figure 1-11. CN8223 Logic Diagram
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
Receive Clock Input I
Receive Clock In PECL I
Receive Serial In PECL I
Receive Input I
Transmit Clock Input I
Transmit Clock In PECL I
Transmit Input I
10
11,12
20,21
15–19,
154,155
22,25
30
23,24
32
RXCKI Line Framer/PHY TCLKO
Interface
RXCKI_HS±
RXIN_HS±
TXOUT[8:0]
31
33–36,
42,43,
56–58
RXIN[8:0]
TXCKI
TXCKI_HS±
TXIN
TCLKO_HS± 28,29
TXOUT_HS± 38,39
LOCD 122
O Transmit Clock Output
O Transmit Outputs
O Transmit Clock Out PECL
O Transmit Serial Out PECL
O Loss of Cell Delineation
Transmit Overhead I
Bus In
44–51
Framing Overhead
Interface
TXOVH[7:0]
RXOVH[7:0]
RMRKR[1:0]
ROVH_CLK[1:0]
TOVH_CLK
TMRKR
2–5,
156–159 O Receive Overhead Bus Out
8,9
O Receive Overhead Markers
6,7
O Receive Overhead Clocks
55
O Transmit Overhead Clock
52
O Transmit Overhead Marker
FIFO Data Bus In I
FIFO Control Input I
98–105,
108
109–116
UTOPIA/FIFO
Interface
FDAT_IN[8:0]
FDAT_OUT[8:0]
FCTRL_IN[7:0]
FCTRL_OUT[16:0]
143–145,
148–153 O FIFO Data Bus Out
124–132,
135–142 O FIFO Control Outputs
8/16-Bit Mode Select I
Processor Clock I
Chip Select I
37 SEL8BIT
97 PRCLK
96 CS~
DL_INT 63
STAT_INT 64
Address Strobe I
94 AS~
Write/Read Control I
Output Enable I
95 W/R~
92 OE~
Microprocessor
Interface
65,
68–79,
Processor Data Bus I/O 82–84 D[15:0]
Address Bus I 85–91 A[7:1]
8 kHz Clock Input I
One-Second Clock Sync I
Receiver Hold Input I
Test Input I
Test Inputs I
Reset I
62
61
123
59
117, 119
118
Clock and Control
8KCKI
ONESECI
RCV_HLD
NTEST
ONESECO 60
TEST1, TEST3
RESET
O FEAC/HDLC Interrupt
O Status/Counter Interrupt
O One-Second Output
I = Input, O = Output
1-18
Conexant
100046C
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