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28222-13 View Datasheet(PDF) - Conexant Systems

Part NameDescriptionManufacturer
28222-13 ATM Transmitter/Receiver with UTOPIA Interface Conexant
Conexant Systems Conexant
28222-13 Datasheet PDF : 161 Pages
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ATM Transmitter/Receiver with UTOPIA Interface
1.0 Product Description
1.7 CN8223 Versions
1.7 CN8223 Versions
Table 1-1 describes the revision history of the Bt8222 device. The Bt8222 is the
predecessor of the CN8223.
Table 1-1. CN8223 Version Descriptions
Baseline version (derived from the Bt8220/1).
All Bt8222KPF functionality plus:
The version number was changed to 62H in the lower byte of the RX_FEAC_VER register.
A software reset was added to CONFIG_5, bit 7. When active high, this is a software equivalent
to pin 118.
Additional overhead insertion capability for STS-3c, STM-1: G1, K2 #1, and Z2 #3 can be
inserted from the external overhead bus. It is controlled by CONFIG_3, bit 6. This is used for
automatic protection switching.
CONFIG_5 has a new receive status indication. CONFIG_5, bit 9 now shows octet G1, bit 5 of
received frames.
All Bt8222KPFB functionality plus:
The version number was changed to 63H in the lower byte of the RX_FEAC_VER register.
The STM-1 C2 transmit octet = 0x13. The C2 receive octet is checked for 0x01 or 0x13.
Bt8222KPFD or
All Bt8222KPFC functionality plus:
The version number was changed to 64H in the lower byte of the RX_FEAC_VER register.
TAXI command strobe timing eliminates the need for an external buffer.
The G1 octet complies with T1.105. The RDI alarm includes bit 7.
The K1/K2 registers were added to provide further support for SONET APS.
HEC integration was removed.
The device complies with a footnote in the UTOPIA specification that allows RxENB~ to be
permanently asserted by the ATM layer.
Disable HEC Check (bit 9 in CELL_VAL) was changed when in UTOPIA mode to be consistent
with FIFO mode.
Payload checking will comply with the ATM standards (lengths 8-44).
When switching to PLCP mode dynamically, the device will go to an OOF state.
FIFO read strobes are forced inactive (high) during hardware or software resets.
All Bt8222KPFD/EPFD functionality plus:
RMRKR[1] was changed to be an 8 kHz output synchronized to the received PLCP frame.
All Bt8222EPFE functionality plus:
Line Loopback (bit 9) in the CONFIG_3 register (0x02) is cleared upon assertion of RESET (pin
Receive STS/SDH pointer processing complies with standards.
Legend for Version Numbers:
K = Temperature range 0 °C to 70 °C
E = 40 °C to 85 °C
PF = Package code = 160-pin PQFP
A/B/C/D/E = Product version
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