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28233-11 View Datasheet(PDF) - Conexant Systems

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28233-11 Datasheet PDF : 161 Pages
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ATM Transmitter/Receiver with UTOPIA Interface
1.0 Product Description
1.5 FIFO Port/UTOPIA Interface
1.5.3 ATM Interface
Each cell is sent to a buffer to allow for header processing before being output to
the ATM interface. The buffer length is 10 octets for G.751 PLCP modes, and 6
octets for HEC alignment. A cell-validoutput is provided to indicate that none
of the enabled error checks detected an error. The UTOPIA internal FIFO or
external circuitry is notified to discard the cell when the valid indication goes
inactive. Idle cells are automatically deleted from the ATM layer output. Parity
and control/delineation signals are provided with each octet at the port interface.
The microprocessor receives status and error counts as cell validation proceeds.
All event and error counters can be programmed to cause an interrupt on
overflow. Reading the interrupt source register allows the microprocessor to
identify overflows and thus update internal counts. All counters can be read by the
microprocessor and are cleared when read.
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