1.0 Product Description
1.2 CN8223 Features
ATM Transmitter/Receiver with UTOPIA Interface
1.2.3 Programmable Parity Protection
Programmable parity protection is available on the system interface. Read and
write strobes allow addressing of up to four distinct data sources and output to
four distinct destinations. Each transmitter port has a programmable priority
level. If the priority levels are the same, the ports are addressed in sequence. Each
receiver port can be programmed with a particular VCI/VPI address for message
routing. Also, VCI/VPI pages can be selected via masking registers. Cells can be
routed to multiple ports for broadcast capability and enhanced test, diagnostic,
and maintenance functions. Also, the cell validation function can be programmed
to correct single-bit header errors.
1.2.4 Test and Diagnostic Functions
The CN8223 provides access to the ATM protocol at all levels for test and
diagnostic functions. Octet-wide simultaneous interfaces are provided for
transmit and receive access to PLCP slots (57 octets), ATM cells (53 octets), cells
without HEC (52 octets), or cell payload only (48 octets). This interface allows
the implementation of test and diagnostic systems. Also, per-cell status can be
optionally provided in place of the HEC octet on Port 3 in a special output mode.
1.2.5 Microprocessor Interface Features
All control and status functions are provided via a direct microprocessor
interface. Also, the microprocessor can control the external framers as required.
The microprocessor interface can be used with either an 8- or 16-bit data bus with
separate address and data signals. Interrupt outputs are provided for status
information on cell and physical layer performance and for data link operations.
The interface is a clocked 8- or 16-bit data interface with an address strobe and a
single read/write control.