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28233-11 View Datasheet(PDF) - Conexant Systems

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28233-11 Datasheet PDF : 161 Pages
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ATM Transmitter/Receiver with UTOPIA Interface
1.0 Product Description
1.2 CN8223 Features
1.2 CN8223 Features
The CN8223 ATM Transmitter/Receiver provides a single-access ATM service
termination for UNI and NNI. It conforms to the following specifications and
ATM Forum UNI Specification 94/0317
Bellcore Specifications TR-TSV-000772, TR-TSV-000773,
TR-NWT-000253, and T1S1/92-185
ITU Recommendations I.432, G.707, G.751, G.832, and Q.921
ETSI draft standards prETS 300 213 and 300 214
Both terminal and switching system interface functions are provided. The
CN8223 provides DS1, E1, DS3, E3, E4, STS-1, and STS-3c (STM-1) Physical
Layer Convergence Procedure (PLCP) functions. It optionally provides for the
generation and validation of AAL3/4 and AAL5 ATM cell payloads. The system
interfaces to the ATM layer through either a UTOPIA-compatible port or a
parallel FIFO port. Provisions for source rate control are included in the
transmitter circuitry.
1.2.1 Internal Framers
Internal framers are included for DS3 C-bit parity format, G.751 E3 format,
G.832 E3 and E4 formats, and STS-1/STS-3c/STM-1 formats. Cell delineation is
via either PLCP framing overhead or G.832 Header Error Control (HEC)
alignment. The CN8223 parallel line interface allows octet recovery/transmission
externally for 100 Mbps TAXI or other interfaces.
The DS1, DS3, E1, and E3 data stream interfaces connect directly to Conexant
framers (Bt8360C for DS1, Bt8510B for E1, Bt8370 for E1/T1 with integral Line
Interface Unit (LIU), and Bt8330B for DS3 and E3). DS1 and DS3 PLCP
functions conform to Bellcore Standard TR-TSV-000773; E1 PLCP conforms to
ETSI draft standard prETS 300 213; and E3 PLCP conforms to ETSI draft
standard prETS 300 214. Transmit and receive functions are provided for all line
rates up to 155 Mbps.
1.2.2 UTOPIA Port
The UTOPIA port conforms to the ATM Forum UTOPIA Level 1 Specification
(Version 2.01) and provides both octet- and cell-based handshaking. The interface
contains transmit and receive buffer FIFOs with a depth of four cells
programmable for reduced latency requirements per ATM Forum document
94/0317. This interface conforms to the Saturn Compliant Interface for ATM
PHY Devices Specification.
The microprocessor can set control registers for insertion of selected header
fields by the transmitter on an individual port basis. Also, the processor can
control insertion of all overhead and can insert errors in selected fields for test
equipment applications.
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