1.0 Product Description
The CN8223 ATM Physical Interface (PHY) device is a transmitter/receiver
which converts several types of frames to ATM cells and vice versa. The device
contains framers for DS3, E3, E4, STS-1, STS-3c, and STM-1. This chapter
provides an overview of the CN8223, describing its primary features and
applications. A block diagram and a logic diagram are included.
1.1 Block Diagram
Figure 1-1 is a detailed block diagram of the CN8223. The host system transmits
octet-wide data to the CN8223 via the UTOPIA or FIFO ports. This data is
assembled into ATM cells by the PHY and formatted for serial line transmission
by the CN8223’s line framers. In the receive direction, serial network data is
framed into octets by either internal or external line framers and passed to the
ATM cell processing block. Octet data is then aligned into ATM cells, checked,
and sent through the UTOPIA or FIFO ports to the host system.
The line framer block connects to external interfaces for line reception and
transmission. The line framer has interfaces for seven data rates and provisions
for external serial or parallel framers. Also included are overhead interfaces, data
links, and event counters.
The HEC/PLCP ATM cell alignment block accepts octet data from the line
framer block. It generates cells for transmission and validates received cells.
Included are HEC/PLCP generators and detectors, data scramblers, and counters.
The FIFO Port/UTOPIA interface communicates with the next layer of ATM
processing, usually residing in the host system. It directs received cell traffic to
four ports, controls transmit priority and rate, and has counters for events and