D 3-State Outputs Drive Bus Lines Directly
D PNP Inputs Reduce dc Loading on Bus
D Hysteresis at Bus Inputs Improves Noise
D Typical Propagation Delay Times Port to
Port, 8 ns
These octal bus transceivers are designed for
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
The devices allow data transmission from the
A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the
direction-control (DIR) input. The output-enable
(OE) input can disable the device so that the
buses are effectively isolated.
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002
SN54LS245 . . . J OR W PACKAGE
SN74LS245 . . . DB, DW, N, OR NS PACKAGE
SN54LS245 . . . FK PACKAGE
3 2 1 20 19
9 10 11 12 13
PDIP – N
0°C to 70°C
SOIC – DW
Tape and reel
SOP – NS
Tape and reel SN74LS245NSR
SSOP – DB Tape and reel SN74LS245DBR
–55°C to 125°C
CDIP – J
CFP – W
LCCC – FK Tube
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.