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SN7414DRG4 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
SN7414DRG4 Hex Schmitt-Trigger Inverters TI
Texas Instruments TI
SN7414DRG4 Datasheet PDF : 35 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
SN5414, SN54LS14, SN7414, SN74LS14
SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Supply voltage, VCC(2)
Input voltage
Junction temperature, TJ
Storage temperature, Tstg
SNx414
SNx4LS14
MIN
MAX
UNIT
7
V
5.5
V
7
150
°C
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage values are with respect to network ground terminal.
6.2 ESD Ratings
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
VALUE
±1500
±2000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
SN5414, SN54LS14
SN7414, SN74LS14
SN5414, SN7414
SN54LS14, SN74LS14
SN5414, SN7414
SN54LS14
SN74LS14
SN5414, SN54LS14
SN7414, SN74LS14
MIN
4.5
4.75
–55
0
NOM
5
5
MAX
5.5
5.25
–0.8
–0.4
16
4
8
125
70
UNIT
V
mA
mA
°C
6.4 Thermal Information
THERMAL METRIC(1)
D (SOIC)
SNx414, SNx4LS14
DB (SSOP)
N (PDIP)
NS (SO)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
ψJB
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
14 PINS
90.1
50.3
44.3
17.9
44.1
14 PINS
105.4
57.3
52.7
22.5
52.2
14 PINS
54.9
42.5
34.7
27.8
34.6
14 PINS
88.8
46.5
47.5
16.8
47.2
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package termal impedance is calculated in accordance with JESD 51-7.
4
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