T89C51RD2-RLWI-M View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

T89C51RD2-RLWI-M

0 to 40 MHz Flash Programmable 8-bit Microcontroller

Atmel Corporation 

T89C51RD2

6.6. Serial I/O Port

The serial I/O port in the T89C51RD2 is compatible with the serial I/O port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous

Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and

reception can occur simultaneously and at different baud rates

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

6.6.1. Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing

bit error detection feature, set SMOD0 bit in PCON register (See Figure 13).

SM0/FE SM1 SM2 REN TB8 RB8 TI

RI SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD0 = 0)

SMOD1 SMOD0 -

POF GF1 GF0 PD IDL PCON (87h)

To UART framing error control

Figure 13. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop

bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit

is not found, the Framing Error bit (FE) in SCON register (See Table 15.) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can

clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,

RI rises on stop bit instead of the last data bit (See Figure 14. and Figure 15.).

RXD

RI

SMOD0=X

FE

SMOD0=1

D0 D1 D2 D3 D4 D5 D6 D7

Start

Data byte

Stop

bit

bit

Figure 14. UART Timings in Mode 1

Rev. F - 15 February, 2001

32

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