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SN54LS73 View Datasheet(PDF) - Motorola => Freescale

Part NameSN54LS73 Motorola
Motorola => Freescale Motorola
DescriptionDUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP


SN54LS73 Datasheet PDF : 3 Pages
1 2 3
SN54 / 74LS73A
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
Min
Typ
Max
Unit
54
4.5
5.0
5.5
V
74
4.75
5.0
5.25
TA
Operating Ambient Temperature Range
54
– 55
25
125
°C
74
0
25
70
IOH
Output Current — High
IOL
Output Current — Low
54, 74
54
74
– 0.4
mA
4.0
mA
8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
VIH
Input HIGH Voltage
Min Typ Max Unit
Test Conditions
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
VIK
VOH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54
0.7
Guaranteed Input LOW Voltage for
74
0.8
V
All Inputs
– 0.65 – 1.5
V
VCC = MIN, IIN = – 18 mA
54
2.5 3.5
74
2.7 3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
V
or VIL per Truth Table
VOL
Output LOW Voltage
IIH
Input HIGH Current
54, 74
74
J, K
Clear
Clock
J, K
Clear
Clock
0.25 0.4
0.35 0.5
20
60
80
0.1
0.3
0.4
V
IOL = 4.0 mA
V
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
µA VCC = MAX, VIN = 2.7 V
mA VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
J, K
Clear, Clock
– 0.4
– 0.8
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
– 20
ICC
Power Supply Current
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
–100
6.0
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay,
Clock to Output
30
45
15
20
15
20
mA
mA
Unit
MHz
ns
ns
VCC = MAX
VCC = MAX
Test Conditions
Figure 1
Figure 1
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
tW
ts
th
Parameter
Clock Pulse Width High
Clear Pulse Width
Setup Time
Hold Time
Limits
Min Typ Max Unit
20
ns
25
ns
20
ns
0
ns
Test Conditions
Figure 1
Figure 2
Figure 1
VCC = 5.0 V
FAST AND LS TTL DATA
5-69
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  TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the clock pulse is HIGH and the bistable will per formaccording to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

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