SN54-74LS90 View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

SN54-74LS90

DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER

ON Semiconductor 

SN54/74LS90 • SN54/74LS92 • SN54/74LS93

FUNCTIONAL DESCRIPTION

The LS90, LS92, and LS93 are 4-bit ripple type Decade,

Divide-By-Twelve, and Binary Counters respectively. Each

device consists of four master/slave flip-flops which are

internally connected to provide a divide-by-two section and a

divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight

(LS93) section. Each section has a separate clock input which

initiates state changes of the counter on the HIGH-to-LOW

clock transition. State changes of the Q outputs do not occur

simultaneously because of internal ripple delays. Therefore,

decoded output signals are subject to decoding spikes and

should not be used for clocks or strobes. The Q0 output of

each device is designed and specified to drive the rated

fan-out plus the CP1 input of the device.

A gated AND asynchronous Master Reset (MR1 • MR2) is

provided on all counters which overrides and clocks and

resets (clears) all the flip-flops. A gated AND asynchronous

Master Set (MS1 • MS2) is provided on the LS90 which

overrides the clocks and the MR inputs and sets the outputs to

nine (HLLH).

Since the output from the divide-by-two section is not

internally connected to the succeeding stages, the devices

may be operated in various counting modes.

LS90

A. BCD Decade (8421) Counter — The CP1 input must be ex-

ternally connected to the Q0 output. The CP0 input receives

the incoming count and a BCD count sequence is pro-

duced.

B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3

output must be externally connected to the CP0 input. The

input count is then applied to the CP1 input and a divide-by-

ten square wave is obtained at output Q0.

C. Divide-By-Two and Divide-By-Five Counter — No external

interconnections are required. The first flip-flop is used as a

binary element for the divide-by-two function (CP0 as the

input and Q0 as the output). The CP1 input is used to obtain

binary divide-by-five operation at the Q3 output.

LS92

A. Modulo 12, Divide-By-Twelve Counter — The CP1 input

must be externally connected to the Q0 output. The CP0 in-

put receives the incoming count and Q3 produces a sym-

metrical divide-by-twelve square wave output.

B. Divide-By-Two and Divide-By-Six Counter —No external

interconnections are required. The first flip-flop is used as a

binary element for the divide-by-two function. The CP1 in-

put is used to obtain divide-by-three operation at the Q1

and Q2 outputs and divide-by-six operation at the Q3 out-

put.

LS93

A. 4-Bit Ripple Counter — The output Q0 must be externally

connected to input CP1. The input count pulses are applied

to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are

performed at the Q0, Q1, Q2, and Q3 outputs as shown in

the truth table.

B. 3-Bit Ripple Counter— The input count pulses are applied

to input CP1. Simultaneous frequency divisions of 2, 4, and

8 are available at the Q1, Q2, and Q3 outputs. Independent

use of the first flip-flop is available if the reset function coin-

cides with reset of the 3-bit ripple-through counter.

FAST AND LS TTL DATA

5-3

Share Link: