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SL74HC166D Ver la hoja de datos (PDF) - System Logic Semiconductor

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SL74HC166D 8-Bit Serial or Parallel-Input/Serial-Output Shift Register SLS
System Logic Semiconductor SLS
SL74HC166D Datasheet PDF : 6 Pages
1 2 3 4 5 6
SL74HC166
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V 25 °C to 85°C 125°C Unit
-55°C
fmax Minimum Clock Frequency (50% Duty Cycle)
(Figures 2 and 4)
2.0 6.0
5.0
4.2 MHz
4.5 31
25
21
6.0 36
28
25
tPLH, tPHL Maximum Propagation Delay, Clock (or Clock
Inhibit) to QH (Figures 2,3 and 4)
2.0 140
175
210
ns
4.5 28
35
42
6.0 24
30
36
tPHL Maximum Propagation Delay , Clear to QH (Figures 2.0 150
200
230
ns
1 and 4)
4.5 30
40
48
6.0 26
34
40
tTLH, tTHL Maximum Output Transition Time, Any Output
2.0 75
95
110
ns
(Figures 1 and 4)
4.5 16
20
25
6.0 14
18
20
CIN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Package)
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
140
pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Symbol
Parameter
V
tsu
Minimum Setup Time, Shift/Load to
2.0
Clock (Figure 3)
4.5
6.0
tsu
Minimum Setup Time, Data before
2.0
Clock (or Clock Inhibit) (Figure 3)
4.5
6.0
tw
Minimum Pulse Width, Clock (or
2.0
Clock Inhibit) (Figure 2)
4.5
6.0
Guaranteed Limit
25 °C to
-55°C
85°C 125°C Unit
80
100
120
ns
16
20
24
14
18
20
80
100
120
ns
16
20
24
14
18
20
80
100
120
ns
16
20
24
14
17
20
SLS System Logic
Semiconductor
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