• after the device is selected with CSB going low, an 8-bit command is received. The
command defines the operations to be performed
• the rising edge of CSB ends all data transfer and resets internal counter and
• if an invalid command is received, no data will be shifted into chip and the MISO
will remain in high impedance state until the falling edge of CSB. This will
reinitialize the serial communication.
• to be able to perform any other command than those listed in Table 1. SPI
commands, the lock register content has to be set correctly. If other command is
feed without correct lock register content, no data will be shifted into chip and the
MISO will remain in high impedance state until the falling edge of CSB.
• data transfer to MOSI continues right after the command is received in all cases
where data is to be written to ASIC’s internal registers
• data transfer out from MISO starts with a falling edge of SCK right after the last bit
of SPI command is sampled in on the rising edge of SCK
• maximum data transfer speed exceeds 500 kHz clock rate
SPI command can be an individual command or a combination of command and data. In
the case of combined command and data, the input data follows uninterruptedly the SPI
command and the output data is shifted out parallel with the input data.
10 11 12 13 14 15
HIGH IM PEDANCE
One command and data transmission over the SPI
After power up the circuit starts up in measure mode. This is the operation mode that is
used in the final application.
Murata Electronics Oy
Doc. Nr. 8225700