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SCA1000-D01 View Datasheet(PDF) - Murata Manufacturing

Part NameDescriptionManufacturer
SCA1000-D01 PRODUCT SPECIFICATION FOR XY-DUAL AXIS ACCELEROMETER Murata
Murata Manufacturing Murata
SCA1000-D01 Datasheet PDF : 18 Pages
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SCA1000-D01
3 SPI Interface
Serial peripheral interface (SPI) is a 4-wire synchronous serial interface. Data communication
is enabled with low active Slave Select or Chip Select wire (CSB). Data is transmitted with 3-
wire interface consisting of serial data input (MOSI), serial data output (MISO) and serial
clock (SCK). Every SPI system consists of one master and one or more slaves, where the
master is defined as the microcomputer that provides the SPI clock, and the slave is any
integrated circuit that receives the SPI clock from the master.
Figure 4.
MASTER
MICROCONTROLLER
DATA OUT (MOSI)
DATA IN (MISO)
SERIAL CLOCK (SCK)
SS0
SS1
SS2
SS3
Typical SPI connection
SLAVE
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
The SPI interface of this ASIC is designed to support almost any micro controller that uses
software implemented SPI. However it is not designed to support any particular hardware
implemented SPI found in many commercial micro controllers. Serial peripheral interface in
this product is used in testing and calibration purposes as well as in the final application. In
normal use some testing and calibration commands are disabled and have not been
documented here. This ASIC operates always as a slave device in the master-slave
operation mode. The data transfer between the master (µP test machine etc.) and ASIC is
performed serially with four wire system.
MOSI
MISO
SCK
CSB
master out slave in
master in slave out
serial clock
chip select (low active)
µP ASIC
ASIC → µP
µP ASIC
µP ASIC
Each transmission starts with a falling edge on CSB and ends with the rising edge. During
the transmission, commands and data are controlled by SCK and CSB according to the
following rules:
commands and data are shifted MSB first LSB last
each output data/status-bits are shifted out on the falling edge of SCK (MISO line)
each bit is sampled on the rising edge of SCK (MOSI line)
Murata Electronics Oy
www.muratamems.fi
Doc. Nr. 8225700
10/18
Rev.C
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