SAA7366 View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
SAA7366 Datasheet PDF : 20 Pages
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Philips Semiconductors
Bitstream conversion ADC for
digital audio systems
Preliminary specification
SAA7366
During standby the following occurs:
• The internal logic clock is disabled
• The serial interface pins are forced to high impedance
• The OVLD output is forced LOW
• The analog circuitry is disabled
• The nominal external analog node voltages are
maintained by a low-power circuit. This feature ensures
a fast recovery from standby mode.
On a LOW-to-HIGH transition the device reverts back to its
normal function. This process takes approximately 32
system clock cycles. Before SDO is enabled the output
data is forced LOW. SDO remains LOW until good data is
available from the decimation filter.
The STD pin has a Schmitt-trigger input. A simple
power-on reset function can be effected using an external
capacitor to VSSD and resistor to VDDD.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDDA
VI
IIK
VO
IO
IDDtot
ISStot
Tamb
Tstg
Ves1
Ves2
PARAMETER
analog supply voltage
DC input voltage
DC input diode current
DC output voltage
DC output source or sink current
total DC supply current
total DC supply current
operating ambient temperature
storage temperature
electrostatic handling
electrostatic handling
CONDITIONS
note 1
note 2
note 3
MIN.
−0.5
−0.5
−
−0.5
−
−
−
−40
−65
−2 000
−200
MAX.
+6.5
+6.5
±20
VDD + 0.5
±20
±0.5
±0.5
+85
+150
+2 000
+200
Notes
1. VSSD and VSSA pins must be externally connected to a common potential.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
UNIT
V
V
mA
V
mA
A
A
°C
°C
V
V
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
CHARACTERISTICS
VDDD = 3.4 to 5.5 V; VDDA = 4.5 to 5.5 V; Tamb = −40 to +85 °C; fs = 18 to 53 kHz; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDA
analog supply voltage
4.5
5.0
5.5
V
IDDA
analog supply current
fs = 48 kHz
−
13
−
mA
VDDD
digital supply voltage
3.4
5.0
5.5
V
IDDD
digital supply current
fs = 48 kHz
−
56
−
mA
Ptot
total power consumption
fs = 48 kHz
−
345
−
mW
May 1994
7
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