Philips Semiconductors
CS-PD Hamburg
1 DOCUMENT INFO
1.1 Revision History
CVIP2
Datasheet
SAA7115
Date:
Version:
10/23/01
0.67
VERSION NO
REVISION
DATE
0.5
5 Oct 2001
0.51
9 Oct 2001
0.52
9 Oct 2001
0.6
10 Oct 2001
0.65
18 Oct 2001
0.66
19 Oct 2001
0.67
23 Oct 2001
DESCRIPTION OF STATUS
Initial Version
Fixed LCBW recommended setting
VBSL setting changed, scaler and PLL2 examples , sect.
16.4 and 16.5 updated
Added application examples
Status at CQS
Minor updates
Fixed application example drawing
BY
H. Lambers
H. Lambers
A. Mittelberg
H. Lambers
H. Lambers
H. Lambers
H. Lambers
2 FEATURES
2.1 Video Acquisition
• Six analog inputs, internal analog source selectors, (e.g.: 6x CVBS or(2 x YC and 2 CVBS) or (1 x YC and 4xCVBS)
• Two built in analog anti-alias filters
• Two improved 9 Bit CMOS analog-to-digital converter in differential CMOS style at two-fold ITU-656 oversampling
(27MHz)
• Fully programmable static gain or automatic gain control (AGC) for the selected CVBS or Y/C channel
• Automatic Clamp Control (ACC) for CVBS, Y and C
• Switchable white Peak Control · Two 9-bit Video CMOS AD Converters, digitized CVBS or Y/C
• signals are available on the expansion port (X-port)
• Requires only one crystal (32.11 MHz or 24.576 MHz) for all standards
• Independent Gain and Offset - adjustment for raw data path
2.2 Combfilter Video Decoder
• Digital PLL for Synchronization and Clock Generation from all Standards and Non Standard Video Sources e.g.
consumer grade VTR
• Automatic detection of 50/60Hz field frequency, and automatic recognition of all common broadcast standards
• Enhanced Horizontal and vertical Sync Detection
• Luminance and chrominance signal processing for
– PAL BGDHIN,
– Combination-PAL N,
– PAL M,
– NTSC M,
– NTSC-Japan,
– NTSC 4.43 and
– SECAM (50 Hz / 60 Hz)
• PAL delay line for correcting PAL phase errors
Confidential - NDA required
Filename: SAA7115_Datasheet.fm
page 6
Last edited by H. Lambers