ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR
1. Basic operation: CMOS output (Active “L”)
(1) When the power supply voltage (VDD) is higher than the release voltage (+VDET), the Nch transistor is OFF and the
Pch transistor is ON to provide VDD (“H”) at the output. Since the Nch transistor N1 in Figure 14 is OFF, the
comparator input voltage is (RB + RC) • VDD .
RA + RB + RC
(2) When the VDD goes below +VDET, the output provides the VDD level, as long as the VDD remains above the detection
voltage −VDET. When the VDD falls below −VDET (point A in Figure 15), the Nch transistor becomes ON, the Pch
transistor becomes OFF, and the VSS level appears at the output. At this time the Nch transistor N1 in Figure 14
becomes ON, the comparator input voltage is changed to RB • VDD .
RA + RB
(3) When the VDD falls below the minimum operating voltage, the output becomes undefined, or goes to the VDD when the
output is pulled up to the VDD.
(4) The VSS level appears when the VDD rises above the minimum operating voltage. The VSS level still appears even
when the VDD surpasses −VDET, as long as it does not exceed the release voltage +VDET.
(5) When the VDD rises above +VDET (point B in Figure 15), the Nch transistor becomes OFF and the Pch transistor
becomes ON to provide VDD level at the output.
*1. Parasiteic diode
Figure 14 Operation 1
Seiko Instruments Inc.