RTL8101 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

RTL8101

REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC’97 CONTROLLER WITH POWER MANAGEMENT

Unspecified 

RTL8101L

REALTEK SINGLE CHIP

FAST ETHERNET CONTROLLER

AND

MC’97 CONTROLLER

WITH POWER MANAGEMENT

RTL8101L

1. Features: ....................................................................... 3

1.1 Ethernet Controller Features: .................................. 3

1.2 MC’97 Controller Features: .................................... 3

2. General Description..................................................... 4

3. Pin Assignment............................................................. 5

4. Pin Description............................................................. 6

4.1 Power Management/Isolation Interface................... 6

4.2 PCI Interface........................................................... 6

4.3 EEPROM Interface ................................................. 7

4.4 Power Pins .............................................................. 8

4.5 LED Interface ......................................................... 8

4.6 Attachment Unit Interface....................................... 8

4.7 AC-Link Pins .......................................................... 8

4.8 Test and Other Pins............................................... 10

5. Ethernet Controller Register Descriptions .............. 11

5.1 Receive Status Register in Rx packet header ........ 13

5.2 Transmit Status Register (TSD0-3)....................... 13

5.3 ERSR: Early Rx Status Register ........................... 14

5.4 Command Register................................................ 14

5.5 Interrupt Mask Register ........................................ 15

5.6 Interrupt Status Register........................................ 15

5.7 Transmit Configuration Register........................... 16

5.8 Receive Configuration Register ............................ 17

5.9 9346CR: 93C46 Command Register..................... 20

5.10 CONFIG 0: Configuration Register 0 ................. 20

5.11 CONFIG 1: Configuration Register 1 ................. 20

5.12 Media Status Register ......................................... 21

5.13 CONFIG 3: Configuration Register3 .................. 22

5.14 CONFIG 4: Configuration Register4 .................. 23

5.15 Multiple Interrupt Select Register....................... 24

5.16 PCI Revision ID.................................................. 24

5.17 TransmitStatusofAllDescriptors(TSAD)Register............. 24

5.18 Basic Mode Control Register.............................. 24

5.19 Basic Mode Status Register ................................ 25

5.20 Auto-negotiation Advertisement Register ........... 25

5.21 Auto-Negotiation Link Partner Ability Register . 26

5.22 Auto-negotiation Expansion Register ................. 27

5.23 Disconnect Counter ............................................ 27

5.24 False Carrier Sense Counter ............................... 27

5.25 NWay Test Register ........................................... 27

5.26 RX_ER Counter.................................................. 27

5.27 CS Configuration Register.................................. 28

5.28 Config5: Configuration Register 5...................... 28

6. MC’97ControllerRegisterandDescriptorDescriptions .......... 30

6.1 The Starting Descriptor Index for LINE-Out........ 30

6.2 The Current Descriptor Index for LINE-Out ........ 30

6.3 The Last Descriptor Index for LINE-Out ............. 30

6.4 LINE-Out DMA Status Register........................... 31

6.5 LINE-Out DMA Control Register ........................ 31

6.6 ResidualSamplesCountinCurrentLINE-OutDescriptorRegister31

6.7 LINE-Out Descriptor Base Address Register ....... 32

6.8 The Starting Descriptor Index for LINE-In .......... 32

6.9 The Current Descriptor Index for LINE-In........... 32

6.10 The Last Descriptor Index for LINE-In.............. 32

6.11 LINE-In DMA Status Register ........................... 32

6.12 LINE-In DMA Control Register......................... 32

6.13 ResidualSamplesCountinCurrentLINE-InDescriptorRegister 33

6.14 Line-In Descriptor Base Address Register ......... 33

6.15 MC’97-Link Control Register ............................ 34

6.16 MC’97-Link Status and Index Register .............. 34

6.17 AC-Link Data Port.............................................. 35

6.18 GPIO Control to MC’97..................................... 35

6.19 Real Time GPIO Input Data From MC’97 ......... 36

6.20 Interrupt Status Register ..................................... 36

6.21 PCI GPIO Setup Register ................................... 37

6.22 PCI GPIO Status Register................................... 39

6.23 Context For Line-Out Descriptor........................ 39

6.24 Context For Line-In Descriptor .......................... 40

6.25 Descriptor Definition.......................................... 40

7. EEPROM (93C46) Contents................................ 42

7.1 Summary of RTL8101L’s EEPROM registers ..... 44

7.2 SummaryofEEPROMPowerManagementregisters........... 44

8. PCI Configuration Space Registers..................... 45

2003/05/28

1

Rev. 1.3

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