RT8223P View Datasheet(PDF) - Richtek Technology
Part Name
Description
Manufacturer
RT8223P Datasheet PDF : 23 Pages
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RT8223P
The average drive current is calculated by the gate charge
at VGS = 5V times the switching frequency. The
instantaneous drive current is supplied by the flying
capacitor between the BOOTx and PHASEx pins. A dead
time to prevent shoot through is internally generated
between high side MOSFET off to the low side MOSFET
on, and the low side MOSFET off to the high side MOSFET
on.
The low side driver is designed to drive high current, low
RDS(ON) N-MOSFET(s). The internal pull-down transist or
that drives LGATEX low is robust, with a 1.5Ω typical on-
resistance. A 5V bias voltage is delivered from the VREG5
supply. The instantaneous drive current is supplied by an
input capacitor connected between VREG5 and GND.
For high current applications, some combinations of high
and low side MOSFETs might be encountered that will
cause excessive gate-drain coupling, which can lead to
efficiency killing, EMI-producing shoot-through currents.
This can be remedied by adding a resistor in series with
BOOTx, which increases the turn-on time of the high side
MOSFET without degrading the turn-off time (Figure 3).
VIN
BOOTx RBOOT
UGATEx
PHASEx
Figure 3. Increasing the UGATEx Rise Time
Soft-Start
The RT8223P provides an internal soft-start function to
prevent large inrush current and output voltage overshoot
when the converter starts up. The soft-start (SS)
automatically begins once the chip is enabled. During soft-
start, it clamps the ramping of internal reference voltage
which is compared with FBx signal. The typical soft-
start duration is 2 ms. A unique PWM duty limit control
that prevents output over voltage during soft-start period
is designed specifically for FBx floating.
UVLO Protection
The RT8223P features VREG5 under voltage lockout
protection (UVLO). When the VREG5 voltage is lower than
3.9V (typ.) and the VREG3 voltage is lower than 2.5V
(typ.), both switch power supplies are shut off. This is
non-latch protection.
Power Good Output (PGOOD)
PGOOD is an open-drain type output and requires a pull-
up resistor. PGOOD is actively held low in soft-start,
standby, and shutdown. It is released when both output
voltages are above 91% of the nominal regulation point.
The PGOOD goes low if either output turns off or is 15%
below its nominal regulator point.
Output Over Voltage Protection (OVP)
The output voltage can be continuously monitored for over
voltage. If the output voltage exceeds 12% of its set voltage
threshold, the over voltage protection is triggered and the
LGATEx low side gate drivers are forced high. This activates
the low side MOSFET switch, which rapidly discharges
the output capacitor and pulls the input voltage downward.
The RT8223P is latched once OVP is triggered and can
only be released by toggling EN, ENTRIPx or cycling VIN.
There is a 5μs delay built into the over voltage protection
circuit to prevent false alarm.
Note that the LGATEx latching high causes the output
voltage to dip slightly negative when energy has been
previously stored in the LC tank circuit. For loads that
cannot tolerate a negative voltage, place a power Schottky
diode across the output to act as a reverse polarity clamp.
If the over-voltage condition is caused by a short in the
high side switch, completely turning on the low side
MOSFET can create an electrical short between the
battery and GND, which will blow the fuse and disconnect
the battery from the output.
Output Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. If the output is less than 52% of its set
voltage threshold, under voltage protection will be triggered,
and then both UGATEx and LGATEx gate drivers will be
forced low. The UVP will be ignored for at least 5ms (typ.)
after start-up or a rising edge on ENTRIPx. Toggle
DS8223P-01 June 2011
www.richtek.com
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