P-DSO-12-6 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

P-DSO-12-6

Dual Low Drop Voltage Regulator

Infineon Technologies 

TLE 4473 GV53

TLE 4473 GV52

Reset and Watchdog Behaviour:

The reset output RO1 is in high-state if the voltage on the delay capacitor CD1 is greater

or equal VDL1. The delay capacitor CD1 is charged with the current IDC1 for output voltages

greater than the reset threshold VRT1. If the output voltage drops below VRT1 (“reset

condition”), the delay capacitor CD1 will be discharged rapidly. If VD1 reaches VDL1, the

reset output RO1 is set to low.

At power-on, the charging process of CD1 starts from 0 V, which leads to the equation

tD, on

=

C-----D---1----×-----V----D---U----1

IDC1

(1)

for the power-on reset delay time.

When the voltage at the delay capacitor has reached VDU1 and RO1 was set to high, the

watchdog circuit is enabled and discharges CD1 with the constant current IDD1.

If there is no rising edge observed at the watchdog input, CD1 will be discharged down to

VDL1, where the reset output RO1 will be set to low and CD1 will be charged again with

the current IDC1 until VD1 reaches VDU1 and reset will be set high again.

If a watchdog pulse (rising edge at watchdog input WI) occurs during the discharge

period, CD1 is charged again and the reset output stays high. After VD1 has reached VDU1,

the periodical cycle starts again.

The watchdog timing is shown in Figure 2. The maximum duration between two

watchdog pulses corresponds to the minimum watchdog trigger time TWI,tr. Higher

capacitances on pin D1 result in larger watchdog trigger time:

TWI,tr max = 0.42 ms/nF × CD1

(2)

If the output voltage Q2 decreases below VRT2 , the external capacitor CD2 is discharged.

When the voltage at this capacitor drops below VDL2, a reset signal is generated at pin

11 (RO2), i.e. the reset output is set to low-level. If the output voltage rises above the

reset threshold, CD2 will be charged with the constant current IDC2. After the power-on-

reset time, the voltage at the capacitor reaches VDU2 and the reset output will be set to

high again. The value of the power-on-reset time can be set within a wide range

depending of the capacitance of CD2 using Equation (1) analogous for Q2.

Data Sheet

3

Rev. 1.0, 2004-07-14

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