PXA300 View Datasheet(PDF) - Actel Corporation
Part Name
Description
Manufacturer
PXA300 Datasheet PDF : 2 Pages
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Storage Solution for Marvell’s PXA300/310 Platform
SD/SDIO Bus Interface Unit:
SD 2.0, SDIO 1.2, MMC3.31, MMC4.2,
and CE-ATA devices communicate with
the host controller through the SD/
MMC Bus Interface Unit (BIU). The BIU
consists of the Command Decoder,
Response Generator, Transmitter/
Receiver, and Power Control/Switch
units. SD1, SD4, and SPI modes are sup-
ported. Other BIU functions include the
16-bit CRC generator and checker for
the data lines, 7-bit CRC generator and
checker for the command and response
lines, interrupt state machine, and BIU
Master state machine.
Advanced DMA:
The controller supports SDMA, ADMA1,
and ADMA2. The Single Operation
DMA (SDMA) algorithm forms a perfor-
mance bottleneck by interruption at
every page boundary. ADMA adopts
the scatter-gather DMA algorithm so
that higher data transfer speed is avail-
able. ADMA provides data transfer
between system memory and the SD
card without interruption of CPU execu-
tion. ADMA can support both 32-bit
and 64-bit system memory addressing.
ADMA1 can support data transfer of
only 4 KB aligned data in system mem-
ory. ADMA2 improves the restriction so
that data of any location and any size
can be transferred in system memory.
AHB/APB Interface:
The Arasan SD2.0/MMC4.2/CE-ATA Host
core provides a Programmed I/O
method in which the ARM host driver
transfers data using the Buffer Data
Port register. The AHB Slave has direct
access to the Host Control registers and
these registers can be programmed by
the ARM processor through the AHB
Slave interface. Data transactions are
performed through the AHB Slave
interface with the Programmed I/O
method. The AHB Interface initiates a
read or write transaction with the
memory if the data transaction is a
DMA data transfer.
MMC4.2/CE-ATA Interface:
The MMC interface conforms with the
MMC system specification 4.2. It sup-
ports 8-bit MMC mode, Error Correction
Code (ECC), MMCplus and MMCmobile
card types. The CE-ATA Host Controller
conforms with CE-ATA Digital Protocol
revision 1.1RC, and with support for CE-
ATA Digital Protocol commands (CMD39
/CMD60 / CMD61). The CE-ATA interface
allows for lower pin count, better
power utilization, voltages tailored to
battery-based applications, and more
efficient command protocol.
About Arasan:
Arasan Chip Systems, Inc. founded in 1995, is a leading supplier of Reusable Intellectual Prop-
erty (IP) cores, semiconductors, and electronic design services. Arasan’s product portfolio is
focused on Bus Interfaces and includes IP for MIPI, USB 1.1 and USB 2.0, PCI, SDIO, and CE-ATA
technologies. Arasan is headquartered in San Jose, California, with design centers in India
and support options available in Taiwan, China, and Europe.
Benefits:
• Fully compliant core with
proven silicon
• Premier direct support from
Arasan core designers
• Easy-to-use industry stan-
dard test environment
• Unencrypted source code
allows easy implementation
• Customer training available
• ReUse Methodology Man-
ual guidelines (RMM) com-
pliant verilog code ensured
using Spyglass
Deliverables:
• RMM Compliant Synthesiz-
able RTL design in Verilog
• Easy-to-use test environment
• Synthesis scripts
• Technical documents
Optional Items:
• SD/SDIO Host Validation
Platform
• SDIO Device Development
Board
• SD/MMC/CE-ATA WinCE
stack
Supported Platforms/Simulators:
• Platforms: Solaris, Unix,
Linux, and Windows® XP
• Verilog simulators: Synopsys
VCS, Cadence NC-Verilog,
MTI ModelSim-Verilog
Copyright 2007 Arasan Chip Systems Inc.
Arasan Chip Systems, Inc. Data Sheet Links:
1150 N. First St. Suite #201
San Jose CA 95112
Phone: 408-282-1600
Fax: 408-282-7800
E-mail: sales@arasan.com
SD/MMC4.2/CE-ATA Host Core:
http://www.arasan.com/datasheets/login.php
For a complete directory of Arasan IPs, please
visit: www.arasan.com
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