ST90158M9 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST90158M9

8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM

STMicroelectronics 

ST90158 - INTERRUPTS

with the highest position in the chain, as shown in

Figure 9

Table 9. Daisy Chain Priority

Highest Position

Lowest Position

INTA0

INTA1

INTB0

INTB1

INTC0

INTC1

INTD0

INTD1

TIMER0

SCI0

SCI1

A/D

TIMER3

TIMER1

INT0/WDT

INT1

INT2/SPI

INT3

INT4/STIM

INT5

INT6/RCCU

INT7

4.4.4 Dynamic Priority Level Modification

The main program and routines can be specifically

prioritized. Since the CPL is represented by 3 bits

in a read/write register, it is possible to modify dy-

namically the current priority value during program

execution. This means that a critical section can

have a higher priority with respect to other inter-

rupt requests. Furthermore it is possible to priori-

tize even the Main Program execution by modify-

ing the CPL during its execution. See Figure 20

Figure 20. Example of Dynamic priority

level modification in Nested Mode

INTERRUPT 6 HAS PRIORITY LEVEL 6

Priority Level

4

ei

INT6

CPL is set to 7

by MAIN program

5

MAIN

CPL is set to 5

6

CPL6 > CPL5:

INT6 pending

INT 6

CPL=6

7

MAIN

CPL=7

4.5 ARBITRATION MODES

The ST9 provides two interrupt arbitration modes:

Concurrent mode and Nested mode. Concurrent

mode is the standard interrupt arbitration mode.

Nested mode improves the effective interrupt re-

sponse time when service routine nesting is re-

quired, depending on the request priority levels.

The IAM control bit in the CICR Register selects

Concurrent Arbitration mode or Nested Arbitration

Mode.

4.5.1 Concurrent Mode

This mode is selected when the IAM bit is cleared

(reset condition). The arbitration phase, performed

during every instruction, selects the request with

the highest priority level. The CPL value is not

modified in this mode.

Start of Interrupt Routine

The interrupt cycle performs the following steps:

– All maskable interrupt requests are disabled by

clearing CICR.IEN.

– The PC low byte is pushed onto system stack.

– The PC high byte is pushed onto system stack.

– If ENCSR is set, CSR is pushed onto system

stack.

– The Flag register is pushed onto system stack.

– The PC is loaded with the 16-bit vector stored in

the Vector Table, pointed to by the IVR.

– If ENCSR is set, CSR is loaded with ISR con-

tents; otherwise ISR is used in place of CSR until

iret instruction.

End of Interrupt Routine

The Interrupt Service Routine must be ended with

the iret instruction. The iret instruction exe-

cutes the following operations:

– The Flag register is popped from system stack.

– If ENCSR is set, CSR is popped from system

stack.

– The PC high byte is popped from system stack.

– The PC low byte is popped from system stack.

– All unmasked Interrupts are enabled by setting

the CICR.IEN bit.

– If ENCSR is reset, CSR is used instead of ISR.

Normal program execution thus resumes at the in-

terrupted instruction. All pending interrupts remain

pending until the next ei instruction (even if it is

executed during the interrupt service routine).

Note: In Concurrent mode, the source priority level

is only useful during the arbitration phase, where it

is compared with all other priority levels and with

the CPL. No trace is kept of its value during the

ISR. If other requests are issued during the inter-

rupt service routine, once the global CICR.IEN is

re-enabled, they will be acknowledged regardless

of the interrupt service routine’s priority. This may

cause undesirable interrupt response sequences.

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