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PSD804F2V-B-70M View Datasheet(PDF) - STMicroelectronics

Part NamePSD804F2V-B-70M ST-Microelectronics
STMicroelectronics ST-Microelectronics
DescriptionConfigurable Memory System on a Chip for 8-Bit Microcontrollers
PSD804F2V-B-70M Datasheet PDF : 110 Pages
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PSD835G2
4.0
PSD8XX
Architectural
Overview
PSD8XX Family
PSD8XX devices contain several major functional blocks. Figure 1 on page 3 shows the
architecture of the PSD8XX device family. The functions of each block are described
briefly in the following sections. Many of the blocks perform multiple functions and are user
configurable.
4.1 Memory
The PSD835G2 contains the following memories:
4 Mbit Flash
A secondary 256 Kbit Flash memory for boot or data
64 Kbit SRAM.
Each of the memories is briefly discussed in the following paragraphs. A more detailed
discussion can be found in section 9.
The 4 Mbit Flash is the main memory of the PSD835G2. It is divided into eight
equally-sized sectors that are individually selectable.
The 256 Kbit secondary Flash memory is divided into four equally-sized sectors. Each
sector is individually selectable.
The 64 Kbit SRAM is intended for use as a scratchpad memory or as an extension to the
microcontroller SRAM. If an external battery is connected to the PSD8XX’s Vstby pin, data
will be retained in the event of a power failure.
Each block of memory can be located in a different address space as defined by the user.
The access times for all memory types includes the address latching and DPLD decoding
time.
4.2 PLDs
The device contains two PLD blocks, each optimized for a different function, as shown in
Table 2. The functional partitioning of the PLDs reduces power consumption, optimizes
cost/performance, and eases design entry.
The Decode PLD (DPLD) is used to decode addresses and generate chip selects for the
PSD835G2 internal memory and registers. The CPLD can implement user-defined logic
functions. The DPLD has combinatorial outputs. The CPLD has 16 Output MicroCells
and 8 combinatorial outputs. The PSD835G2 also has 24 Input MicroCells that can be
configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus
and are differentiated by their output destinations, number of Product Terms, and
MicroCells.
The PLDs consume minimal power by using Zero-Power design techniques. The speed and
power consumption of the PLD is controlled by the Turbo Bit in the PMMR0 register and
other bits in the PMMR2 registers. These registers are set by the microcontroller at runtime.
There is a slight penalty to PLD propagation time when invoking the non-Turbo bit.
4.3 I/O Ports
The PSD835G2 has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F and G).
Each I/O pin can be individually configured for different functions. Ports can be configured
as standard MCU I/O ports, PLD I/O, or latched address outputs for microcontrollers using
multiplexed address/data busses.
The JTAG pins can be enabled on Port E for In-System Programming (ISP). Ports F and
G can also be configured as a data port for a non-multiplexed bus.
4.4 Microcontroller Bus Interface
The PSD835G2 easily interfaces with most 8-bit microcontrollers that have either
multiplexed or non-multiplexed address/data busses. The device is configured to respond
to the microcontroller’s control signals, which are also used as inputs to the PLDs. Section
9.3.5 contains microcontroller interface examples.
Table 2. PLD I/O Table
Name
Decode PLD
Complex PLD
Abbreviation
DPLD
CPLD
Inputs
82
82
Outputs
17
24
Product Terms
43
150
5
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