PSD804F2V-A-70UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD804F2V-A-70UI Datasheet PDF : 110 Pages
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CNTL0,
CNTL1,
CNTL2
PROG.
MCU BUS
INTRF.
AD0 – AD15
ADIO
PORT
PF0 – PF7
PROG.
PORT
PORT
F
PG0 – PG7
PROG.
PORT
PORT
G
CLKIN
ADDRESS/DATA/CONTROL BUS
PLD
INPUT
BUS
PAGE
REGISTER
EMBEDDED
ALGORITHM
4 MBIT MAIN FLASH
MEMORY
8 SECTORS
SECTOR
FLASH DECODE
PLD (DPLD)
SELECTS
82
SECTOR
SELECTS
256 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
SRAM SELECT
64 KBIT BATTERY
BACKUP SRAM
PERIP I/O MODE SELECTS
CSIOP
RUNTIME CONTROL
AND I/O REGISTERS
82
FLASH ISP CPLD
(CPLD)
8 EXT CS to PORT C or F
16 OUTPUT MICRO⇔CELLS
PORT A & B
CLKIN
24 INPUT MICRO⇔CELLS
PORT A ,B & C
MICRO⇔CELL FEEDBACK OR PORT INPUT
CLKIN
PORT F
GLOBAL
CONFIG. &
SECURITY
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
*Additional address lines can be brought into PSD via Port A, B, C, D, or F.
POWER
MANGMT
UNIT
VSTDBY
(PE6)
PROG.
PORT PA0 – PA7
PORT
A
PROG.
PORT
PORT
B
PB0 – PB7
PROG.
PORT
PORT
C
PC0 – PC7
PROG.
PORT
PORT
D
PD0 – PD3
PROG.
PORT
PORT
E
PE0 – PE7
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