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PSD804F2V-A-20B81 View Datasheet(PDF) - STMicroelectronics

Part NamePSD804F2V-A-20B81 ST-Microelectronics
STMicroelectronics ST-Microelectronics
DescriptionConfigurable Memory System on a Chip for 8-Bit Microcontrollers
PSD804F2V-A-20B81 Datasheet PDF : 110 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
PSD8XX Family
8.0
Register Bit
Definition
(cont.)
PSD835G2
JTAG Enable Register
Bit 7
Bit 6
Bit 5
Bit 4
*
*
*
*
Bit definitions:
JTAG_Enable 1 = JTAG Port is Enabled.
0 = JTAG Port is Disabled.
Page Register
Bit 7
Pgr7
Bit 6
Pgr6
Bit 5
Pgr5
Bit 4
Pgr4
Bit 3
*
Bit 3
Pgr3
Bit 2
*
Bit 2
Pgr2
Bit 1
*
Bit 0
JTAG_Enable
Bit 1
Pgr1
Bit 0
Pgr0
Bit definitions:
Configure Page input to PLD. Default Pgr[7:0] = 00.
PMMR0 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
*
*
PLD
PLD
PLD
Mcells clk array-clk Turbo
*Not used bit should be set to zero.
Bit definitions: (default is 0)
Bit 1 0 = Automatic Power Down (APD) is disabled.
1 = Automatic Power Down (APD) is enabled.
*
APD
enable
Bit 3 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
Bit 4 0 = CLKIN input to the PLD AND array is connected.
Every CLKIN change will power up the ZPLD when Turbo bit is off.
1 = CLKIN input to PLD AND array is disconnected, saving power.
Bit 5 0 = CLKIN input to the PLD MicroCells is connected.
1 = CLKIN input to the PLD MicroCells is disconnected, saving power.
Bit 0
*
PMMR1 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
PLD
PLD
PLD
PLD
PLD
*
*
array WRh array Ale array Cntl2 array Cntl1 array Cntl0
*Not used bit should be set to zero.
Bit definitions (default is 0):
Bit 0 0 = Address A[7:0] are connected into the PLD array.
1 = Address A[7:0] are blocked from the PLD array, saving power.
Note: in XA mode, A3-0 come from PF3-0 and A7-4 come from ADIO7-4.
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
1 = Cntl0 input to the PLD AND array is disconnected, saving power.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
1 = Cntl1 input to the PLD AND array is disconnected, saving power.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
1 = Cntl2 input to the PLD AND array is disconnected, saving power.
Bit 5 0 = Ale input to the PLD AND array is connected.
1 = Ale input to the PLD AND array is disconnected, saving power.
Bit 6 0 = WRh/DBE input to the PLD AND array is connected.
1 = WRh/DBE input to the PLD AND array is disconnected, saving power.
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