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PSD804F2V-A-15JI View Datasheet(PDF) - STMicroelectronics

Part NamePSD804F2V-A-15JI ST-Microelectronics
STMicroelectronics ST-Microelectronics
DescriptionConfigurable Memory System on a Chip for 8-Bit Microcontrollers


PSD804F2V-A-15JI Datasheet PDF : 110 Pages
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PSD835G2
Table 5.
PSD835G2
Pin
Descriptions
(cont.)
PSD8XX Family
Pin*
(TQFP
Pin Name Pkg.)
PA0-PA7 51-58
PB0-PB7 61-68
PC0-PC7 41-48
PD0
79
PD1
80
PD2
1
PD3
2
PE0
71
PE1
72
PE2
73
Type
I/O
CMOS
or Open
Drain
I/O
CMOS
or Open
Drain
I/O
CMOS
or Slew
Rate
I/O
CMOS
or Open
Drain
I/O
CMOS
or Open
Drain
I/O
CMOS
or Open
Drain
I/O
CMOS
or Open
Drain
I/O
CMOS
or Open
Drain
I/O
CMOS
or Open
Drain
I/O
CMOS
or Open
Drain
Description
Port A, PA0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port
2. CPLD MicroCell (MCell A0-7) output.
3. Latched, transparent or registered PLD input.
Port B, PB0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. CPLD MicroCell (MCell B0-7) output.
3. Latched, transparent or registered PLD input.
Port C, PC0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. External chip select (ECS0-7) output.
3. Latched, transparent or registered PLD input.
Port D pin PD0 can be configured as:
1. ALE or AS input — latches addresses on ADIO0-15 pins
2. AS input — latches addresses on ADIO0-15 pins on the
rising edge.
3. Input to the PLD.
4. Transparent PLD input.
Port D pin PD1 can be configured as:
1. MCU I/O
2. Input to the PLD.
3. CLKIN clock input — clock input to the CPLD
MicroCells, the APD power down counter and CPLD
AND Array.
Port D pin PD2 can be configured as:
1. MCU I/O
2. Input to the PLD.
3. CSI input — chip select input. When low, the CSI enables
the internal PSD memories and I/O. When high, the
internal memories are disabled to conserve power. CSI
trailing edge can get the part out of power-down mode.
Port D pin PD3 can be configured as:
1. MCU I/O
2. Input to the PLD.
Port E, PE0. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Latched address output.
3. TMS input for JTAG/ISP interface.
Port E, PE1. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Latched address output.
3. TCK input for JTAG/ISP interface (Schmidt Trigger).
Port E, PE2. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Latched address output.
3. TDI input for JTAG/ISP interface.
9
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Introduction
The PSD8XX series of Programmable Microcontroller (MCU) Peripherals brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD8XX devices combine many of the peripheral functions found in MCU based applications:
  • 4 Mbit of Flash memory
  • A secondary Flash memory for boot or data
  • Over 3,000 gates of Flash programmable logic
  • 64 Kbit SRAM
  • Reconfigurable I/O ports
  • Programmable power management.

FEATURES SUMMARY
■ 5 V±10% Single Supply Voltage:
■ Up to 4 Mbit of Primary Flash Memory (8 uniform sectors)
■ 256Kbit Secondary Flash Memory (4 uniform sectors)
■ Up to 64 Kbit SRAM
■ Over 3,000 Gates of PLD: DPLD and CPLD
■ 52 Reconfigurable I/O ports
■ Enhanced JTAG Serial Port
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 Erase/Write Cycles of PLD

 

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