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PSD804F2V-A-70MI View Datasheet(PDF) - STMicroelectronics

Part NamePSD804F2V-A-70MI ST-Microelectronics
STMicroelectronics ST-Microelectronics
DescriptionConfigurable Memory System on a Chip for 8-Bit Microcontrollers
PSD804F2V-A-70MI Datasheet PDF : 110 Pages
First Prev 101 102 103 104 105 106 107 108 109 110
PSD8XX Family
14.0
Pin Capacitance
PSD835G2
TA = 25 °C, f = 1 MHz
Symbol
Parameter 1
Conditions Typical2 Max Unit
CIN
Capacitance (for input pins only)
VIN = 0 V
4
6 pF
COUT
Capacitance (for input/output pins)
VOUT = 0 V
8
12 pF
CVPP
Capacitance (for CNTL2/VPP)
VPP = 0 V
18
25 pF
NOTES: 1. These parameters are only sampled and are not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.
15.0
Figure 46.
AC Testing
Input/Output
Waveform
3.0V
0V
TEST POINT
1.5V
16.0
Figure 47.
AC Testing
Load Circuit
DEVICE
UNDER TEST
2.01 V
195
CL = 30 pF
(INCLUDING
SCOPE AND JIG
CAPACITANCE)
17.0
Programming
Upon delivery from ST, the PSD835G2 device has all bits in the PLDs and
memories in the 1or high state. The configuration bits are in the 0or low state. The
code, configuration, and PLDs logic are loaded through the procedure of programming.
Information for programming the device is available directly from ST. Please
contact your local sales representative. (See the last page.)
102
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