PSD503B1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD503B1

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics 

PSD5XX Family

Introduction

(cont.)

The Peripheral PLD (PPLD) generates outputs to the Counter/Timer unit and the Interrupt

Controller. The PPLD outputs to the Counter/Timer enable, disable, or trigger counting or

time capture. The PPLD outputs to the Interrupt Controller enables the user to define

conditions for interrupt generation.

The Counter/Timer unit provides four 16-bit highly flexible Counter/Timers. Each has five

modes of operation: pulse, waveform, event counting, time capture, and watchdog

(real-time clock). Each Counter/Timer can be programmed to count up or down. The inputs

to the Counter/Timer, which enable/disable counting or trigger an operation, can originate

from the PPLD directly or directly from the pins. The maximum operating frequency of each

counter is 7.5 MHz. The input clock can be divided (by up to 280) before driving the

Counter/Timer unit using the 4 to 280 prescaler.

The Interrupt Controller has eight levels of priority encoding. It accepts four user-defined

interrupts and four terminal counts from the Counter/Timer. Each interrupt can be

individually masked and configured to be level or edge sensitive. A 3-bit interrupt vector is

generated that can be read by the microcontroller. The serviced interrupt will be cleared

automatically after the microcontroller has read the interrupt vector.

The PSD5XX has 40 I/O pins that are divided among 5 ports. Each I/O pin can be

individually configured to provide many functions, including the following:

• MCU I/O

• ZPLD I/O

• Latched address output (for MCUs with multiplexed data bus)

• Special function I/O (Counter/Timer and Interrupts)

• Data bus (for MCUs with non-multiplexed data bus).

The PSD5XX can easily interface with virtually any 8- or 16-bit microcontroller with a

multiplexed or non-multiplexed bus. All of the MCU control signals are connected to the

ZPLDs, enabling the user to generate signals for external devices. The PSD5XX can

generate a reset output based on the RESET input (includes hysteresis).

The PSD5XX provides between 256 Kbits and 1 Mbit of EPROM that is divided in to four

equal-sized blocks. Each block can occupy a different address location, allowing for

versatile address mapping. The access time of the EPROM includes the address latching

and DPLD decoding.

The PSD5XX has an optional 16 Kbit SRAM that can be battery-backed by connecting a

battery to the Vstby pin. The battery will protect the contents of the SRAM in the event of a

power failure. Therefore, you can place data in the optional SRAM that you want to keep

after the power is switched off. Power switch-over to the battery automatically occurs when

Vcc drops below Vstby.

A four-bit Page Register enables easy access to the I/O section, EPROM, and SRAM for

microcontrollers with limited address space. The Page Register outputs are connected to

the ZPLDs and thus can also be used for external paging schemes.

Please refer to the revision block at

the end of this document for updated

information.

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