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ZPSD503B1-C-15J View Datasheet(PDF) - STMicroelectronics

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ZPSD503B1-C-15J Datasheet PDF : 153 Pages
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9.2
Bus
Interface
PSD5XX Family
The Bus Interface is very flexible and can be configured to interface to most
microcontrollers with no glue logic. Table 4 lists some of the bus types to which the Bus
Interface is able to interface.
Table 4. Typical Microcontroller Bus Types
Multiplexed
Data Bus
Width
Bus Control
Signals
Mux
Mux /Non-mux
Mux
Mux
Non-mux
Non-mux
Non-mux
Non-mux
Non-mux
Non-mux
8
WR, RD, PSEN, A0
8/16
R/W, E, BHE, A0
8/16
WR, RD, BHE, A0
16
WRL, RD, WRH, A0
16
R/W, LDS, UDS
8/16
R/W, DS, SIZ0, A0
16
R/W, DS, BHE, BLE
8
RD, WR
16
R/W, E, LSTRB, A0
16
R/W, DS
Microcontroller
8031/80C51
68HC11
80C196/80C186
80C196SP
68302
68340
68330, 68331
68HC05C
68HC12
68HC16
9.2.1 Bus Interface Configuration
The Bus Interface Logic is user configurable. The type of bus interface is specified by
the user in the PSDsoft software (PSD configuration). The bus control input pins have
multi-function capabilities. By choosing the right configuration, the PSD5XX is able to
interface to most microcontrollers, including the ones listed in Table 4. In Table 5, the
names of the bus control input signal pins and their multiple functions are shown. For
example, Pin PE0 can be configured by the PSD configuration software to perform any one
of the five functions. Examples on the interface between the PSD5XX and some typical
microcontrollers are shown in following sections.
Table 5. Alternate Pin Functions
Pin Name
Pin
Function
1
Pin
Function
2
RD
RD
E
WR
WR
R/W
PE0
BHE
PSEN
PE1
ALE
AD0
A0
BLE
Pin
Function
3
DS
WRL
WRH
Pin
Function
4
LDS
UDS
Pin
Function
5
SIZ0
9.2.2 PSD5XX Interface To a Multiplexed Bus
Figure 14 shows a typical connection to a microcontroller with a multiplexed bus. The ADIO
port of the PSD5XX is connected directly to the microcontroller address/data bus
(AD0-AD15 for 16 bit bus). The ALE input signal latches the address lines internally. In a
read bus cycle, data is driven out through the ADIO Port transceivers after the specified
access time. The internal ADIO Port connection for a 16 bit multiplexed bus is shown in
Figure 15. The ADIO port is in tri-state mode if none of the PSD5XX internal devices are
selected.
29
 

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