PM8315-PI View Datasheet(PDF) - PMC-Sierra

Part Name

Description

Manufacturer

PM8315-PI

HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MULTIPLEXER

PMC-Sierra 

STANDARD PRODUCT

DATASHEET

PMC-1981125

ISSUE 7

5.2 M13 Multiplexer Mode Block Diagram

PM8315 TEMUX

HIGH DENSITY T1/E1 FRAMER WITH

INTEGRATED VT/TU MAPPER AND M13 MUX

Figure 4 shows the TEMUX, configured as a M13 multiplexer, connected to a

synchronous MVIP system side bus. In this example the TEMUX provides

synchronous access to the fully channelized T1s (access to all DS0s)

multiplexed into the DS3. There is also synchronous MVIP access to all channel

associated signaling channels (CAS). An additional MVIP interface can be used

to provide synchronous access to the common channel signaling channels

(CCS), although this same information is available within the data MVIP signals.

Figure 4 - M13 Multiplexer Block Diagram

TOPS

Timing Options

T J AT

Digital Jitter

A ttenuator

T1-XBAS/E1-T RAN

BasicTransm itter:

Frame Generation,

Alarm Insertion,

Signaling Ins ertion,

Trunk Conditioning

TPSC

P e r-D S 0

C o n tro lle r

ESIF

Egress

S y ste m

Interface

XCLK

CTCLK

CMV8MCLK

CMVFPB

MV ED [1:7]

CASED[1:7]

CCSED

T IC LK

TCLK

TPOS/TDAT

T N EG /T MF P

RCLK

R PO S /R D AT

RN EG /RLCV

XBOC

Tx

FEAC

T D PR

Tx

H DLC

B3ZS

Encode

T R AN

DS3

Transm it

F ra m e r

B3ZS

Decode

FRM R

DS3

Receiv e

F ra m e r

RBOC

Rx

FEAC

R DLC

Rx

HDLC

PM ON

Perf.

M o n it o r

#1

M X23

M23

MU X/

DEMUX

FRMR MX12

DS2 M12

Framer MUX/

DEMUX

One of Seven

FRMR/M12s

XBOC

Bit Oriented

Code

G en erator

TDPR

HDLC

Transmitter

PM ON

Performance

Mo n it o r

Counters

RDLC

HDLC

Receiver

T1-APRM

Auto

Performance

Response

Monitor

RBOC

Bit Oriented

Code

Detector

ALM I

Alarm

In te g r a to r

PRBS

P a tte rn

Gener-

ator/

Detector

R J AT

Digital Jitter

A ttenu ator

One of 28 T1 or

21 E1 Fram ers

T1/E1-FR MR

F ra m e

Alignm ent,

A la rm

E x tra ctio n

FRAM

Framer RAM

ELST

Elastic

Store

S IG X

S ig n a lin g

E xtrac tor

RPSC

P e r-D S 0

C o n tro lle r

ISIF

Ingress

S y ste m

Interface

MVID[1:7]

C AS ID [1:7]

CCSID

CIFP

CICLK/CMVFPC

RECVCLK1

RECVCLK2

5.3 VT/TU Mapper Only Mode Block Diagram

Figure 5 shows the TEMUX configured as a VT or TU mapper. In this mode the

TEMUX bypasses the T1 and E1 framers and provides access for up to 28

independent unframed 1.544Mb/s streams or 21 independent unframed

2.048Mb/s streams. The 1.544Mb/s and 2.048Mb/s streams can be accessed on

the system side as clock and data as shown in Figure 5, or they can be

accessed via the SBI bus. The T1 or E1 framers and performance monitoring

blocks can be used to monitor the passing traffic in either the ingress or egress

direction. The M13 Multiplexer mode operates in much the same way as the VT

and TU mapper shown in Figure 5.

PROPRIETARY AND CONFIDENTIAL

23

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