PIC18F45J50-I/SPQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F45J50-I/SPQTP
Microchip Technology
PIC18F45J50-I/SPQTP Datasheet PDF : 562 Pages
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Pin Diagrams
28-Pin SPDIP/SOIC/SSOP(1)
MCLR
1
RA0/AN0/C1INA/ULPWU/RP0
2
RA1/AN1/C2INA/RP1
3
RA2/AN2/VREF-/CVREF/C2INB
4
RA3/AN3/VREF+/C1INB
5
VDDCORE/VCAP(2)
6
RA5/AN4/SS1/HLVDIN/RCV/RP2
7
VSS
8
OSC1/CLKI/RA7
9
OSC2/CLKO/RA6
10
RC0/T1OSO/T1CKI/RP11
11
RC1/T1OSI/UOE/RP12
12
RC2/AN11/CTPLS/RP13
13
VUSB
14
PIC18F46J50 FAMILY
= Pins are up to 5.5V tolerant
28
RB7/KBI3/PGD/RP10
27
RB6/KBI2/PGC/RP9
26
RB5/KBI1/SDI1/SDA1/RP8
25
RB4/PMA1/KBI0/SCK1/SCL1/RP7
24
RB3/AN9/CTED2/VPO/RP6
23
RB2/AN8/CTED1/VMO/REFO/RP5
22
RB1/AN10/RTCC/RP4
21
RB0/AN12/INT0/RP3
20
VDD
19
VSS
18
RC7/RX1/DT1/SDO1/RP18
17
RC6/TX1/CK1/RP17
16
RC5/D+/VP
15
RC4/D-/VM
28-Pin QFN(1,3)
RA2/AN2/VREF-/CVREF/C2INB
RA3/AN3/VREF+/C1INB
VDDCORE/VCAP(2)
RA5/AN4/SS1/HLVDIN/RCV/RP2
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
28 27 26 25 24 23 22
1
21
2
20
3
19
4 PIC18F2XJ50 18
5
17
6
16
7
15
8 9 1011 12 13 14
RB3/AN9/CTED2/VPO/RP6
RB2/AN8/CTED1/VMO/REFO/RP5
RB1/AN10/RTCC/RP4
RB0/AN12/INT0/RP3
VDD
VSS
RC7/RX1/DT1/SDO1/RP18
Legend:
Note 1:
2:
3:
RPn represents remappable pins.
Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be
dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 10-13
and Table 10-14, respectively. For details on configuring the PPS module, see Section 10.7 “Peripheral
Pin Select (PPS)”.
See Section 27.3 “On-Chip Voltage Regulator” for details on how to connect the VDDCORE/VCAP pin.
For the QFN package, it is recommended that the bottom pad be connected to VSS.
2011 Microchip Technology Inc.
DS39931D-page 5
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