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PIC16CR56AT-LPISP View Datasheet(PDF) - Microchip Technology

Part NamePIC16CR56AT-LPISP Microchip
Microchip Technology Microchip
DescriptionEPROM/ROM-Based 8-bit CMOS Microcontroller Series


PIC16CR56AT-LPISP Datasheet PDF : 192 Pages
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3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16C5X family can be
attributed to a number of architectural features com-
monly found in RISC microprocessors. To begin with,
the PIC16C5X uses a Harvard architecture in which
program and data are accessed on separate buses.
This improves bandwidth over traditional von Neumann
architecture where program and data are fetched on
the same bus. Separating program and data memory
further allows instructions to be sized differently than
the 8-bit wide data word. Instruction opcodes are 12
bits wide making it possible to have all single word
instructions. A 12-bit wide program memory access
bus fetches a 12-bit instruction in a single cycle. A two-
stage pipeline overlaps fetch and execution of instruc-
tions. Consequently, all instructions (33) execute in a
single cycle except for program branches.
The PIC16C54/CR54 and PIC16C55 address 512 x 12
of program memory, the PIC16C56/CR56 address
1K x 12 of program memory, and the PIC16C57/CR57
and PIC16C58/CR58 address 2K x 12 of program
memory. All program memory is internal.
The PIC16C5X can directly or indirectly address its
register files and data memory. All special function reg-
isters including the program counter are mapped in the
data memory. The PIC16C5X has a highly orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16C5X simple yet efficient. In addition, the learning
curve is reduced significantly.
PIC16C5X
The PIC16C5X device contains an 8-bit ALU and work-
ing register. The ALU is a general purpose arithmetic
unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
The ALU is 8 bits wide and capable of addition, subtrac-
tion, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature. In two-operand instructions, typically
one operand is the W (working) register. The other
operand is either a file register or an immediate con-
stant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respec-
tively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1
(for PIC16C54/56/58) and Table 3-2 (for PIC16C55/
57).
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 9
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GENERAL DESCRIPTION
The PIC16C5X from Microchip Technology is a family of low cost, high performance, 8-bit fully static, EPROM/ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle except for program branches which take two cycles. The PIC16C5X delivers performance in an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly.

Devices Included in this Data Sheet:
• PIC16C54
• PIC16CR54
• PIC16C55
• PIC16C56
• PIC16CR56
• PIC16C57
• PIC16CR57
• PIC16C58
• PIC16CR58

High-Performance RISC CPU:
• Only 33 single word instructions to learn
• All instructions are single cycle except for program branches which are two-cycle
• Operating speed: DC - 40 MHz clock input
                        DC - 100 ns instruction cycle
• 12-bit wide instructions
• 8-bit wide data path
• Seven or eight special function hardware registers
• Two-level deep hardware stack
• Direct, indirect and relative addressing modes for data and instructions

Peripheral Features:
• 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler
• Power-on Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
• Programmable Code Protection
• Power saving SLEEP mode
• Selectable oscillator options:
   - RC: Low cost RC oscillator
   - XT: Standard crystal/resonator
   - HS: High speed crystal/resonator
   - LP: Power saving, low frequency crystal

CMOS Technology:
• Low power, high speed CMOS EPROM/ROM technology
• Fully static design
• Wide operating voltage and temperature range:
   - EPROM Commercial/Industrial 2.0V to 6.25V
   - ROM Commercial/Industrial 2.0V to 6.25V
   - EPROM Extended 2.5V to 6.0V
   - ROM Extended 2.5V to 6.0V
• Low power consumption
   - < 2 mA typical @ 5V, 4 MHz
   - 15 A typical @ 3V, 32 kHz
   - < 0.6 A typical standby current
      (with WDT disabled) @ 3V, 0°C to 70°C

 

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