PCA9500D View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCA9500D Datasheet PDF : 26 Pages
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NXP Semiconductors
PCA9500
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
slave address (memory)
word address
data
SDA S 1 0 1 0 A2 A1 A0 0 A
A
AP
START condition
Fig 10. Byte write
R/W acknowledge
from slave
acknowledge
from slave
acknowledge STOP condition.
from slave Write to the memory
is performed.
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7.4.1.2 Page write
A page write is initiated in the same way as the byte write. If after sending the first word of
data, the STOP condition is not received, the PCA9500 considers subsequent words as
data. After each data word the PCA9500 responds with an acknowledge and the two least
significant bits of the memory address field are incremented. Should the master not send
a STOP condition after four data words, the address counter will return to its initial value
and overwrite the data previously written. After the receipt of the STOP condition the
inputs will behave as with the byte write during the internal write cycle.
slave address (memory)
SDA S 1 0 1 0 A2 A1 A0 0 A
word address
data to memory
A
DATA n
A
data to memory
DATA n + 3
AP
START condition
R/W acknowledge
from slave
Fig 11. Page write
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
STOP condition.
Write to the memory is performed.
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7.4.2 Read operations
PCA9500 read operations are initiated in an identical manner to write operations with the
exception that the memory slave address R/W bit is set to ‘1’. There are three types of
read operations: current address read, random read and sequential read.
7.4.2.1 Current address read
The PCA9500 contains an internal address counter that increments after each read or
write access and as a result, if the last word accessed was at address ‘n’, then the
address counter contains the address ‘n + 1’.
When the PCA9500 receives its memory slave address with the R/W bit set to one it
issues an acknowledge and uses the next eight clocks to transmit the data contained at
the address stored in the address counter. The master ceases the transmission by issuing
the STOP condition after the eighth bit. There is no ninth clock cycle for the acknowledge.
See Figure 12.
PCA9500_4
Product data sheet
Rev. 04 — 15 April 2009
© NXP B.V. 2009. All rights reserved.
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