PCA9500BS View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCA9500BS Datasheet PDF : 26 Pages
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NXP Semiconductors
PCA9500
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
7. Functional description
Refer also to Figure 1 “Block diagram of PCA9500”.
write pulse
data from shift register
power-on reset
read pulse
data to shift register
DQ
FF
CI
S
100 µA
DQ
FF
CI
S
Fig 5. Simplified schematic diagram of each I/O
VDD
IO0 to IO7
VSS
to interrupt logic
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7.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9500 is shown in Figure 6. Internal pull-up resistors
are incorporated on the hardware selectable address pins.
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
slave address
0 1 0 0 A2 A1 A0 R/W
fixed
hardware
programmable
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a. I/O expander
Fig 6. PCA9500 slave addresses
slave address
1 0 1 0 A2 A1 A0 R/W
fixed
b. Memory
hardware
programmable
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7.2 Control register
The PCA9500 contains a single 8-bit register called the Control register, which can be
written and read via the I2C-bus. This register is sent after a successful acknowledgment
of the slave address. It contains the I/O operation information.
PCA9500_4
Product data sheet
Rev. 04 — 15 April 2009
© NXP B.V. 2009. All rights reserved.
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