PCA9500 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCA9500 Datasheet PDF : 26 Pages
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NXP Semiconductors
PCA9500
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
12. Dynamic characteristics
Table 6. Dynamic characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
I2C-bus timing[1] (see Figure 22)
fSCL
SCL clock frequency
tSP
pulse width of spikes that must be
suppressed by the input filter
-
-
400
kHz
-
-
50
ns
tBUF
bus free time between a STOP and START
condition
1.3
-
-
µs
tSU;STA
tHD;STA
tr
tf
tSU;DAT
tHD;DAT
tVD;DAT
set-up time for a repeated START condition
hold time (repeated) START condition
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
data set-up time
data hold time
data valid time
SCL LOW to
data output
0.6
-
0.6
-
-
-
-
-
250
-
0
-
-
-
-
µs
-
µs
0.3
µs
0.3
µs
-
ns
-
ns
1.0
µs
tSU;STO
set-up time for STOP condition
Port timing
0.6
-
-
µs
tv(Q)
data output valid time
tsu(D)
data input set-up time
th(D)
data input hold time
Power-up timing
CL ≤ 100 pF
-
-
CL ≤ 100 pF
0
-
CL ≤ 100 pF
4
-
4
µs
-
µs
-
µs
tpu(R)
read power-up time
tpu(W)
write power-up time
Write cycle limits (see Figure 23)
[2] -
-
1
ms
[2] -
-
5
ms
Tcy(W)
write cycle time
[3] -
5
10
ms
[1] All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input
voltage swing of VSS to VDD.
[2] tpu(R) and tpu(W) are the delays required from the time VDD is stable until the specified operation can be initiated. These parameters are
guaranteed by design.
[3] Tcy(W) is the maximum time that the device requires to perform the internal write operation.
Table 7. Non-volatile storage specifications
Parameter
memory cell data retention
number of memory cell write cycles
Specification
10 years minimum
100,000 cycles minimum
PCA9500_4
Product data sheet
Rev. 04 — 15 April 2009
© NXP B.V. 2009. All rights reserved.
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