PCA9500 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

PCA9500

8-bit I2C and SMBus I/O port with 2-kbit EEPROM

Philips Electronics 

Philips Semiconductors

8-bit I2C and SMBus I/O port with 2-kbit EEPROM

Product data sheet

PCA9500

NON-VOLATILE STORAGE SPECIFICATIONS

PARAMETER

Memory cell data retention

Number of memory cell write cycles

SPECIFICATION

10 years minimum

100,000 cycles minimum

I2C-BUS TIMING CHARACTERISTICS

SYMBOL

PARAMETER

I2C-bus timing (see Figure 20; Note 2)

MIN.

TYP.

MAX.

UNIT

fSCL

SCL clock frequency

—

—

400

kHz

tSW

tolerable spike width on bus

—

—

50

ns

tBUF

bus free time

1.3

—

—

µs

tSU;STA START condition set-up time

0.6

—

—

µs

tHD;STA START condition hold time

0.6

—

—

µs

tr

SCL and SDA rise time

—

—

0.3

µs

tf

SCL and SDA fall time

—

—

0.3

µs

tSU;DAT data set-up time

250

—

—

ns

tHD;DAT data hold time

0

—

—

ns

tVD;DAT SCL LOW to data out valid

—

—

1.0

µs

tSU;STO STOP condition set-up time

0.6

—

—

µs

NOTE:

2. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input

voltage swing of VSS to VDD.

PORT TIMING CHARACTERISTICS

SYMBOL

PARAMETER

tpv

Output data valid; CL ≤ 100 pF

tps

Input data setup time; CL ≤ 100 pF

tph

Input data hold time; CL ≤ 100 pF

handbook, full pagewidth START

PROTOCOL

CONDITION

(S)

t SU;STA

BIT 7

MSB

(A7)

SCL

t BUF

tr

SDA

MIN

—

0

4

BIT 6

(A6)

1 / f SCL

tf

TYP

MAX

UNIT

—

4

µs

—

—

µs

—

—

µs

BIT 0

LSB

(R/W)

ACKNOWLEDGE

(A)

STOP

CONDITION

(P)

t HD;STA

t SU;DAT

t HD;DAT

Figure 20.

t VD;DAT

MBD820

t SU;STO

SW00561

2004 Sep 30

14

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