P89LPC9321 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC9321

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

NXP Semiconductors. 

NXP Semiconductors

P89LPC9321

8-bit microcontroller with accelerated two-clock 80C51 core

7.30.4 Using flash as data storage

The flash code memory array of this device supports individual byte erasing and

programming. Any byte in the code memory array may be read using the MOVC

instruction, provided that the sector containing the byte has not been secured (a MOVC

instruction is not allowed to read code memory contents of a secured sector). Thus any

byte in a non-secured sector may be used for non-volatile data storage.

7.30.5 Flash programming and erasing

Four different methods of erasing or programming of the flash are available. The flash may

be programmed or erased in the end-user application (IAP) under control of the

application’s firmware. Another option is to use the ICP mechanism. This ICP system

provides for programming through a serial clock/serial data interface. As shipped from the

factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for

the device to be programmed in circuit through the serial port. The flash may also be

programmed or erased using a commercially available EPROM programmer which

supports this device. This device does not provide for direct verification of code memory

contents. Instead, this device provides a 32-bit Cyclic Redundancy Check (CRC) result on

either a sector or the entire user code space.

Remark: When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and flash

erase/program is blocked.

7.30.6 ICP

ICP is performed without removing the microcontroller from the system. The ICP facility

consists of internal hardware resources to facilitate remote programming of the

P89LPC9321 through a two-wire serial interface. The NXP ICP facility has made in-circuit

programming in an embedded application - using commercially available programmers -

possible with a minimum of additional expense in components and circuit board area. The

ICP function uses five pins. Only a small connector needs to be available to interface your

application to a commercial programmer in order to use this feature. Additional details

may be found in the P89LPC9321 User manual.

7.30.7 IAP

IAP is performed in the application under the control of the microcontroller’s firmware. The

IAP facility consists of internal hardware resources to facilitate programming and erasing.

The NXP IAP has made in-application programming in an embedded application possible

without additional components. Two methods are available to accomplish IAP. A set of

predefined IAP functions are provided in a Boot ROM and can be called through a

common interface, PGM_MTP. Several IAP calls are available for use by an application

program to permit selective erasing and programming of flash sectors, pages, security

bits, configuration bytes, and device ID. These functions are selected by setting up the

microcontroller’s registers before making a call to PGM_MTP at FF03H. The Boot ROM

occupies the program memory space at the top of the address space from FF00H to

FEFFH, thereby not conflicting with the user program memory space.

In addition, IAP operations can be accomplished through the use of four SFRs consisting

of a control/status register, a data register, and two address registers. Additional details

may be found in the P89LPC9321 User manual.

P89LPC9321_1

Product data sheet

Rev. 01 — 9 December 2008

© NXP B.V. 2008. All rights reserved.

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