NXP Semiconductors
P89LPC9321
8-bit microcontroller with accelerated two-clock 80C51 core
TOR2
compare value
timer value
0
non-inverted
inverted
Fig 9. Symmetrical PWM
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7.22.7 Alternating output mode
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating
pairs for bridge drive control. In this mode the output of these PWM channels are
alternately gated on every counter cycle.
TOR2
COMPARE VALUE A (or C)
COMPARE VALUE B (or D)
TIMER VALUE
0
PWM OUTPUT (OCA or OCC)
Fig 10. Alternate output mode
PWM OUTPUT (OCB or OCD)
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7.22.8 PLL operation
The PWM module features a Phase Locked Loop that can be used to generate a
CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module
provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal
frequency is 1 MHz or higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and
generates an output signal of 32 times the input frequency. This signal is used to clock the
timer. The user will have to set a divider that scales PCLK by a factor from 1 to 16. This
divider is found in the SFR register TCR21. The PLL frequency can be expressed as
shown in Equation 1:
PLL frequency = (--P-N---C---+-L---K-1----)
(1)
Where: N is the value of PLLDV3:0.
P89LPC9321_1
Product data sheet
Rev. 01 — 9 December 2008
© NXP B.V. 2008. All rights reserved.
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