P89LPC9321FN View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC9321FN

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

NXP Semiconductors. 

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Table 4. Special function registers …continued

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

addr. MSB

LSB

Reset value

Hex Binary

WDL

Watchdog load C1H

FF

1111 1111

WFEED1

Watchdog

feed 1

C2H

WFEED2

Watchdog

feed 2

C3H

[1] All ports are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reflects the cause of the P89LPC9321 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on

reset value is x011 0000.

[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.

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