89LPC925 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

89LPC925

8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter

Philips Electronics 

Philips Semiconductors

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Remark: During a power-up sequence, the RPE selection is overridden and this pin

will always function as a reset input. An external circuit connected to this pin

should not hold this pin LOW during a power-on sequence as this will keep the

device in reset. After power-up this input will function either as an external reset

input or as a digital input as defined by the RPE bit. Only a power-up reset will

temporarily override the selection defined by RPE bit. Other sources of reset will not

override the RPE bit.

Remark: During a power cycle, VDD must fall below VPOR (see Table 8 “DC electrical

characteristics” on page 39) before power is reapplied, in order to ensure a power-on

reset.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user configured via UCFG1);

• Power-on detect;

• Brownout detect;

• Watchdog Timer;

• Software reset;

• UART break character detect reset.

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can

read this register to determine the most recent reset source. These flag bits can be

cleared in software by writing a ‘0’ to the corresponding bit. More than one flag bit

may be set:

• During a power-on reset, both POF and BOF are set but the other flag bits are

cleared.

• For any other reset, previously set flag bits that have not been cleared will remain

set.

8.16.1 Reset vector

Following reset, the P89LPC924/925 will fetch instructions from either address 0000h

or the Boot address. The Boot address is formed by using the Boot Vector as the high

byte of the address and the low byte of the address = 00h.

The Boot address will be used if a UART break reset occurs, or the non-volatile Boot

Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on

(see P89LPC924/925 User’s Manual). Otherwise, instructions will be fetched from

address 0000H.

8.17 Timers/counters 0 and 1

The P89LPC924/925 has two general purpose counter/timers which are upward

compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to

operate either as timers or event counter. An option to automatically toggle the T0

and/or T1 pins upon timer overflow has been added.

In the ‘Timer’ function, the register is incremented every machine cycle.

9397 750 13459

Product data

Rev. 02 — 15 June 2004

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

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