Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Reset can be triggered from the following sources:
• External reset pin (during power-up or if user configured via UCFG1)
• Power-on detect
• Brownout detect
• Watchdog Timer
• Software reset
• UART break character detect reset (P80LPC903).
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can
read this register to determine the most recent reset source. These flag bits can be
cleared in software by writing a ‘0’ to the corresponding bit. More than one flag bit
may be set:
• During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
• For any other reset, previously set flag bits that have not been cleared will remain
set.
8.16 Timers/counters 0 and 1
The P89LPC901/902/903 has two general purpose timers which are similar to the
standard 80C51 Timer 0 and Timer 1. These timers have four operating modes
(modes 0, 1, 2, and 3). Modes 0, 1, and 2 are the same for both Timers. Mode 3 is
different.
8.16.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured
as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
8.16.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
8.16.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload.
Mode 2 operation is the same for Timer 0 and Timer 1.
8.16.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When
Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.
8.16.5 Mode 6 (P89LPC901)
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
9397 750 12293
Product data
Rev. 04 — 21 November 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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